万年历模块
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity wannianli is
port( preset:in std_logic; clk:in std_logic; jiaoshi:in std_logic;
d_in:in integer range 1 to 31; m_in:in integer range 1 to 12;
y_in:in integer range 2012 to 2030; data: out integer range 1 to 31; month:out integer range 1 to 12; year:out integer range 2012 to 2030; tixing:out std_logic; co:out std_logic); end wannianli;
architecture a of wannianli is
signal yue:integer range 1 to 12:=11;
signal nian:integer range 2012 to 2030:=2012; signal ri:integer range 1 to 31:=26; signal qm:integer range 28 to 31; begin process(yue,nian) begin case yue is
when 1=>qm<=31; when 2 =>
if(((nian mod 4)=0 and (nian mod 100)/=0) or (nian mod 400)=0) then qm<=29; else qm<=28; end if;
when 3 =>qm <=31; when 4 =>qm<=30; when 5 =>qm<=31; when 6 =>qm<=30; when 7 =>qm<=31; when 8 =>qm<=31; when 9 =>qm<=30; when 10 =>qm<=31; when 11 =>qm<=30; when 12 =>qm<=31;
when others =>null;
end case ;
end process;
process(clk,preset) begin if preset='0' then
yue <=11 ; nian<=2012;
ri<=26; else
if (((nian mod 4)=0 and (nian mod 100)/=0) or (nian mod 400)=0) then tixing<='1'; else tixing<='0'; end if;
if ((yue=5 and ri=1) or (yue=10 and ri=1 )
or (yue=1 and ri=1) or (yue=8 and ri=15) or (yue=1 and ri=15)) then co<='1';
else co<='0'; end if;
if clk'event and clk='1' then
if(ri=qm) then ri<=1; if(yue=12)then yue<=1;nian<=nian+1; else yue<=yue+1; end if;
elsif(ri ri<=d_in;yue<=m_in;nian<=y_in; elsif clk'event and clk='1' then if(ri=qm) then ri<=1; if(yue=12)then yue<=1;nian<=nian+1; else yue<=yue+1; end if; elsif(ri end if; end process; month<=yue; year<=nian; data<=ri; end a; 万年历testbench文件 LIBRARY ieee ; USE ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY testbench IS END testbench; ARCHITECTURE a OF testbench IS SIGNAL preset : std_logic := '0' ; SIGNAL clk : std_logic := '1' ; signal co: std_logic; SIGNAL tixing:std_logic; signal jiaoshi:std_logic:='1'; SIGNAL d_in: integer range 1 to 31:=2; SIGNAL m_in: integer range 1 to 12:=2; SIGNAL y_in: integer range 2012 to 2030:=2013; signal yue:integer range 1 to 12:=11; signal nian:integer range 2012 to 2030:=2012; signal ri:integer range 1 to 31:=26; COMPONENT wannianli port( preset:in std_logic; clk:in std_logic; jiaoshi:in std_logic:='1'; d_in:in integer range 1 to 31; m_in:in integer range 1 to 12; y_in:in integer range 2012 to 2030; data: out integer range 1 to 31; month:out integer range 1 to 12; year:out integer range 2012 to 2030; tixing:out std_logic; co:out std_logic); END COMPONENT ; BEGIN process begin wait for 50ns; clk <= not clk; end process; process begin jiaoshi<=not jiaoshi ; wait for 3000ns; end process; preset <= '1' after 20ns; d_in <=2 after 10ns; m_in <=2 after 10ns; y_in <=2013 after 10ns; test:wannianli PORT MAP ( jiaoshi=>jiaoshi, d_in =>d_in, m_in =>m_in, y_in =>y_in, clk=> clk, tixing=>tixing, co=>co, preset=> preset, month=>yue, year=>nian, data=>ri) ; END a; 日模块 library ieee; use ieee.std_logic_1164.all; entity ri is port(clk :in std_logic; preset : in std_logic; data : out integer range 1 to 31; co : out std_logic); end ri; architecture a of ri is signal s :integer range 1 to 31; begin process(clk,preset) begin if preset ='0' then s<=1; elsif (clk'event and clk='1') then if s<31 then s<=s+1; else s<=1; end if; if s=31 then co<='1'; else co<='0'; end if; end if ; end process; data <=s; end a; 日模块testbench文件 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY testbench IS END testbench; ARCHITECTURE a OF testbench IS SIGNAL data : integer :=26 ; signal co : std_logic:='0'; SIGNAL preset : std_logic := '0' ; SIGNAL clk : std_logic := '1' ; COMPONENT ri port(clk :in std_logic; preset : in std_logic; data : out integer range 1 to 31; co : out std_logic); END COMPONENT ; BEGIN process begin wait for 50ns; clk <= not clk; end process; preset <= '1' after 20ns; test:ri PORT MAP ( clk => clk, preset => preset, co => co, data => data) ; END a; 月模块 library ieee; use ieee.std_logic_1164.all;