end component;
component wannianli is
port( preset:in std_logic; clk:in std_logic; jiaoshi:in std_logic;
d_in:in integer range 1 to 31; m_in:in integer range 1 to 12;
y_in:in integer range 2012 to 2030; data: out integer range 1 to 31; month:out integer range 1 to 12; year:out integer range 2012 to 2030; tixing:out std_logic; co:out std_logic); end component;
component naozhong is
port ( clk,preset:in std_logic;----??????? hour: in integer range 0 to 23; data: in integer range 1 to 31; month:in integer range 1 to 12;
year:in integer range 2012 to 2030;---??????? ri:in integer range 1 to 31:=26; shi: in integer range 0 to 23:=14; yue:in integer range 1 to 12:=11;
nian: in integer range 2012 to 2030:=2012; ----??????? music:out std_logic);----?????? end component;
component zhuanhuan is port (preset:in std_logic;
hour: in integer range 0 to 23; data: in integer range 1 to 31; month:in integer range 1 to 12; year:in integer range 2012 to 2030; shi: out integer range 0 to 23:=14; ri:out integer range 1 to 31:=26; yue:out integer range 1 to 12:=11;
nian: out integer range 2012 to 2030:=2012); end component; signal b:std_logic; signal c:std_logic;
signal d:integer range 0 to 23:=14; signal e:std_logic;
signal f:integer range 1 to 31:=26; signal g:integer range 1 to 12:=11;
signal h:integer range 2012 to 2030:=2012;
begin
--u1:fenpin port map(clk=>a,clk_1hz=>b,clk_100hz=>c);
u2:shi port map(preset=>vcc,clk=>a,jiaoshi=>js,h_in=>j,hour=>d,co=>e); u3:wannianli port map(preset=>vcc,clk=>a,jiaoshi=>js,d_in=>k,m_in=>l,y_in=>m,data=>f,month=>g,year=>h,tixing=>runnian,co=>chuantong); u4:naozhong port map(preset=>vcc_m,clk=>a,hour=>d,data=>f,month=>g,year=>h,shi=>s,ri=>r,yue=>y,nian=>n,music=>naozhong_out); u5:zhuanhuan port map(preset=>vcc,hour=>d,data=>f,month=>g,year=>h,shi=>hour_out,ri=>data_out,yue=>month_out,nian=>year_out); end rtl;
顶层模块testbench文件
LIBRARY ieee ;
USE ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY testbench IS END testbench;
ARCHITECTURE a OF testbench IS signal a: std_logic:='1'; signal vcc: std_logic:='0'; signal vcc_m: std_logic:='0'; signal js: std_logic:='0';
signal j:integer range 0 to 23:=13; signal k: integer range 1 to 31:=2; signal l: integer range 1 to 12:=2;
signal m: integer range 2012 to 2030:=2013; signal s: integer range 0 to 23:=1; signal r: integer range 1 to 31:=1; signal y:integer range 1 to 12:=1;
signal n: integer range 2012 to 2030:=2013; signal hour_out: integer range 0 to 23:=14; signal data_out: integer range 1 to 31:=26; signal month_out: integer range 1 to 12:=11;
signal year_out: integer range 2012 to 2030:=2012; signal naozhong_out: std_logic; signal runnian: std_logic; signal chuantong: std_logic; COMPONENT dzz
port( a:in std_logic; vcc:in std_logic; vcc_m:in std_logic; js:in std_logic;
s: in integer range 0 to 23; r: in integer range 1 to 31; y:in integer range 1 to 12; n:in integer range 2012 to 2030; j:in integer range 0 to 23; k:in integer range 1 to 31; l:in integer range 1 to 12;
m:in integer range 2012 to 2030; hour_out:out integer range 0 to 23; data_out: out integer range 1 to 31; month_out:out integer range 1 to 12; year_out:out integer range 2012 to 2030; naozhong_out:out std_logic; runnian:out std_logic; chuantong:out std_logic); END COMPONENT ; BEGIN process begin
wait for 40ns; a <= not a; end process; process begin wait for 300ns;
vcc_m <= not vcc_m; end process; process begin
wait for 5000ns; js<=not js; end process;
j<= 13 after 20ns; k<= 2 after 20ns; l<= 2 after 20ns; m<= 2013 after 20ns; vcc <= '1' after 10ns; s <= 1 after 10ns; r <= 1 after 10ns; y <= 1 after 10ns;
n <= 2013 after 10ns; test:dzz
PORT MAP (
js => js, j => j, k => k, l => l, m => m, a => a, vcc => vcc, vcc_m => vcc_m, s => s, r => r, y => y, n => n,
hour_out => hour_out, data_out => data_out, month_out => month_out, year_out => year_out,
naozhong_out => naozhong_out, runnian => runnian, chuantong => chuantong); END a;