entity yue is
port(clk :in std_logic; preset : in std_logic;
month : out integer range 1 to 12; co : out std_logic); end yue;
architecture a of yue is
signal s :integer range 1 to 12; begin
process(clk,preset) begin
if preset ='0' then s<=1;
elsif (clk'event and clk='1') then if s<12 then s<=s+1; else s<=1; end if;
if s=12 then co<='1'; else co<='0'; end if; end if ;
end process; month <=s; end a;
月模块testbench文件
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY testbench IS END testbench;
ARCHITECTURE a OF testbench IS SIGNAL month : integer :=11 ; signal co : std_logic:='0';
SIGNAL preset : std_logic := '0' ; SIGNAL clk : std_logic := '1' ; COMPONENT yue port(clk :in std_logic;
preset : in std_logic;
month : out integer range 1 to 12; co : out std_logic); END COMPONENT ; BEGIN process
begin
wait for 50ns; clk <= not clk; end process;
preset <= '1' after 20ns; test:yue
PORT MAP ( clk => clk,
preset => preset, co => co,
month => month) ; END a;
年模块
library ieee;
use ieee.std_logic_1164.all; entity nian is
port(clk :in std_logic; preset : in std_logic;
year : out integer range 2012 to 2030; co : out std_logic); end nian;
architecture a of nian is
signal s :integer range 2012 to 2030; begin
process(clk,preset) begin
if preset ='0' then s<=2012; elsif (clk'event and clk='1') then if s<2030 then s<=s+1; else s<=2012; end if;
if s=2030 then co<='1'; else co<='0'; end if; end if ;
end process; year <=s; end a;
年模块testbench文件
library ieee;
use ieee.std_logic_1164.all; entity nian is
port(clk :in std_logic; preset : in std_logic;
year : out integer range 2012 to 2030; co : out std_logic); end nian;
architecture a of nian is
signal s :integer range 2012 to 2030; begin
process(clk,preset) begin
if preset ='0' then s<=2012; elsif (clk'event and clk='1') then if s<2030 then s<=s+1; else s<=2012; end if;
if s=2030 then co<='1'; else co<='0'; end if; end if ;
end process; year <=s; end a;
闹钟模块
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity naozhong is
port (clk,preset:in std_logic;----时钟、使能信号 hour: in integer range 0 to 23; data: in integer range 1 to 31; month:in integer range 1 to 12;
year:in integer range 2012 to 2030;---输入的设定时间 ri:in integer range 1 to 31:=26; shi: in integer range 0 to 23:=14; yue:in integer range 1 to 12:=11;
nian: in integer range 2012 to 2030:=2012;
----输入的实时时间
music:out std_logic);----音乐使能信号 end naozhong;
architecture rtl of naozhong is
signal temp:integer range 0 to 23:=0; begin
process (clk,preset) begin
if (clk'event and clk='1') then----判断设定时间和实时时间是否相等 if ((year=nian)and(data=ri)and(month=yue)and(hour=shi)and(preset='1')) music<='1';
if (hour=5) then temp<=0 ;else
temp<=hour+1;----当相等时自动计时一分钟 end if;
elsif (preset='0') then music<='0';----按停止键闹钟停止 end if;
if (temp=shi) then music<='0';----不按停止键一分钟自动停止 end if; end if;
end process ; end rtl;
then
过渡模块
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity zhuanhuan is port (preset:in std_logic;
hour: in integer range 0 to 23; data: in integer range 1 to 31; month:in integer range 1 to 12; year:in integer range 2012 to 2030; shi: out integer range 0 to 23:=14; ri:out integer range 1 to 31:=26; yue:out integer range 1 to 12:=11;
nian: out integer range 2012 to 2030:=2012); end zhuanhuan;
architecture a of zhuanhuan is
signal y0:integer range 0 to 23:=14; signal y1:integer range 1 to 31:=26; signal y2:integer range 1 to 12:=11;
signal y3:integer range 2012 to 2030:=2012; begin
process (preset,hour,data,month,year) begin
--case hour is
if (preset='0')then y0<=14 ; y1<=26 ; y2<=11 ; y3<=2012; else y0<=hour;y1<=data;y2<=month;y3<=year; end if;
end process;
shi<=y0; ri<=y1; yue<=y2; nian<=y3; end a;
顶层模块
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity dzz is
port( a:in std_logic; vcc:in std_logic; vcc_m:in std_logic; js:in std_logic;
s: in integer range 0 to 23; r: in integer range 1 to 31; y:in integer range 1 to 12; n:in integer range 2012 to 2030; j:in integer range 0 to 23; k:in integer range 1 to 31; l:in integer range 1 to 12;
m:in integer range 2012 to 2030; hour_out:out integer range 0 to 23; data_out: out integer range 1 to 31; month_out:out integer range 1 to 12; year_out:out integer range 2012 to 2030; naozhong_out:out std_logic; runnian:out std_logic; chuantong:out std_logic); end dzz;
architecture rtl of dzz is --component fenpin is --port (clk:in std_logic;
----- clk_1hz,clk_100hz:buffer std_logic); --end component; component shi is
port(clk :in std_logic; preset : in std_logic; jiaoshi: in std_logic;
h_in:in integer range 0 to 23; hour : out integer range 0 to 23; co : out std_logic);