output reg sec );
endmodule module cnt60( input wire clk,
input wire clr, input wire clk0, reg q1;
always @(posedge clk) begin if(q1==1) begin q1<=0;
sec<=~sec; //得到1Hz信号 end else q1<=q1+1; end
output reg [3:0]cnt60_an, output reg [6:0]cnt60_q,
output reg carry );
reg [3:0]cntl;
reg [3:0]cnth;
reg [19:0]clkdiv; //初始化 initial begin cntl=8; cnth=5; end
//60进制计数器
always @(posedge clk ) begin carry=0; cntl=cntl+1; if(cntl==9) begin
cntl=0; cnth=cnth+1; end
if(cnth==5&&cntl==9)
begin cntl=0; cnth=0;
carry=1; //carry是60进制计数器的进位 end end wire s;
reg [3:0]di=10; assign s=clkdiv[19];
always@(*) case(s) 0:di=cntl; 1:di=cnth; endcase
always@(*) case(di)
0:cnt60_q=7'b0000001; 1:cnt60_q=7'b1001111; 2:cnt60_q=7'b0010010; 3:cnt60_q=7'b0000110;
4:cnt60_q=7'b1001100; 5:cnt60_q=7'b0100100; 6:cnt60_q=7'b0100000; 7:cnt60_q=7'b0001111; 8:cnt60_q=7'b0000000; 9:cnt60_q=7'b0000100; default:
begin
cnt60_q=7'b0000001; end
endcase
always@(*) begin
cnt60_an=4'b1111; cnt60_an[s]=0; end
always@(posedge clk0 or posedge clr) begin if(clr==1)
clkdiv=0; else
clkdiv=clkdiv+1; end
endmodule （2）约束文件 NET \NET \
NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \NET \