begin
cnt60_an=4'b1111; cnt60_an[s]=0; end
always@(posedge clk0 or posedge clr) begin if(clr==1) clkdiv=0; else
clkdiv=clkdiv+1; end
endmodule （2）约束文件 NET \NET \
NET \NET \NET \NET \NET \
NET \NET \NET \NET \NET \NET \NET \NET \3．数字钟
（1）VERILOG程序 module top( input wire clk1, input wire clk2, output wire [3:0]an, output wire [6:0]atog );
wire [6:0]minut; wire [5:0]hou; wire [3:0]min0; wire [2:0]min1; wire [3:0]h0; wire [1:0]h1;
wire [3:0]digit;
count_1 counter(clk1,minut,hou);
count_to_num editor(minut,hou,min0,min1,h0,h1); led_enable decoder(clk2,min0,min1,h0,h1,an,digit); seven_led show(digit,atog); endmodule
module count_1( input wire clk, output reg [6:0]minute, output reg [5:0]hour );
initial begin minute=0; hour=0; end
always @(posedge clk) begin
if(minute<59) minute<=minute+1; else begin minute<=0;
if(hour<23) hour<=hour+1; else hour<=0; end end
//always @(posedge clk) //begin
//if(hour<23) hour<=hour+1; //else hour<=0; //end Endmodule
module count_to_num( input wire [6:0]minute, input wire [5:0]hour, output reg [3:0]min0, output reg [2:0]min1, output reg [3:0]h0, output reg [1:0]h1 ); always @(*) begin
if(hour<10) begin h1<=0;h0<=hour; end
else if(hour<20&&hour>=10) begin h1<=1;h0<=hour-10; end else begin h1<=2;h0<=hour-20; end end always @(*) begin
if(minute<10) begin min1<=0;min0<=minute; end
else if(minute<20&&minute>=10) begin min1<=1;min0<=minute-10; end else if(minute<30&&minute>=20) begin min1<=2;min0<=minute-20; end else if(minute<40&&minute>=30) begin min1<=3;min0<=minute-30; end else if(minute<50&&minute>=40) begin min1<=4;min0<=minute-40; end else begin min1<=5;min0<=minute-50; end end endmodule
module led_enable( input wire clk, input wire [3:0]min0, input wire [2:0]min1, input wire [3:0]h0, input wire [1:0]h1, output reg [3:0]en, output reg [3:0]digit