www.altera.com101InnovationDrive,SanJose,CA951342014.08.18AlteraLVDSSERDESIPCoreUserGuide
SubscribeSendFeedbackug_altera_lvdsTheAlteraLVDSSERDESIPCoreconfigurestheserializer/deserializer(SERDES)anddynamicphasealignment(DPA)blocks.TheIPcorealsosupportsLVDSchannelsplacement,legalitychecks,andLVDSchannel-relatedrulechecks.
TheAlteraLVDSSERDESIPcoreisonlyavailableforArria10devices.ForArriaV,CycloneV,and
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StratixVdevices,followthestepsinMigratingYourALTLVDS_TXandALTLVDS_RXIPCoresonpage25tomigrateyourIP.
RelatedInformation
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?LVDSSERDESTransmitter/Receiver(ALTLVDS_TXandALTLVDS_RX)MegafunctionsUserGuide
Features
YoucanconfigurethefeaturesofAlteraLVDSSERDESIPcorethroughtheIPParameterEditorinthe
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QuartusIIsoftware.TheAlteraLVDSSERDESIPcorefeatureincludestheALTLVDS_RXandALTLVDS_TXIPcoresfeaturessupportedinStratixVdevices,suchas:??????
Parameterizabledatachannelwidths
Parameterizableserializer/deserializer(SERDES)factorsRegisteredinputandoutputportsPLLcontrolsignals
Dynamicphasealignment(DPA)modeSoftclockdatarecovery(CDR)mode
FunctionalModes
ThistableliststhefunctionalmodesfortheAlteraLVDSSERDESIPcore.
Table1:FunctionalModesfortheAlteraLVDSSERDESIPCore
FunctionalMode
Description
TX
Inthismode,theIPcoreconfigurestheSERDESblockasaserializer.APLLgeneratesthefastclock(fclk)andloadenable(loaden)signals.
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ISO9001:2008Registered
2FunctionalDescription
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2014.08.18
FunctionalModeDescription
RXNon-DPAMode
Inthismode,youmustensurethecorrectclock-dataalignment,astheincomingdataiscapturedatthebitslipwiththefclksignal.TheDPAandDPA-FIFOarebypassed.Asinthetransmittermode,thefclksignalisprovidedbyaPLL.
Inthismode,theDPAblockselectsanoptimalphasetosampleincomingdatafromasetofeightDPAclocksrunningatthefclkfrequency,each45°outofphase.TheDPA-FIFO,acircularbuffer,samplestheincomingdatawiththeselectedDPAclockandforwardsthedatatoLVDSclockdomain.ThedatareleasedfromtheDPA-FIFOisthensampledatthebitslipcircuitry,whereitislagged,andthus,realignedtomatchthedesiredwordboundarywhenitisdeserialized.
Toavoidclockmetastabilityissues,afterFIFOresets,waitfortwocoreclockcyclesbeforeresettingthebitslip.
Note:AllRXchannelsmustbeplacedinoneI/Obank,whichsupports
upto24channelsonly.
RXDPA-FIFO
RXSoft-CDRMode
Inthismode,theoptimalDPAclock(DPACLK)isforwardedintotheLVDSclockdomain,whereitisusedasthefclksignal.Thelocalclockgeneratorproducesrx_divfwdclkwhichwillbeforwardedtothecorethroughaPCLKnetwork.Note,thereisalimitationofthenumberofsoft-CDRchannelsduetoPCLKusage.
Note:RXinterfacesmustbeplacedinoneI/Obank,andeachbank
onlyhas12PCLKresources,hence12soft-CDRchannels.Note:Foractualsoft-CDRsupportedchannel,refertotherespective
devicepinoutlist.Under\Tx/RxChannel\therewillbeavalueofformLVDS_
FunctionalDescription
AsingleAlteraLVDSSERDESchannelcontainsaSERDES,abitslipblock,DPAcircuitryforallmodes,ahigh-speedclocktree(LVDSclocktree)andforwardedclocksignalforsoft-CDRmode.YoucanconfiguretheAlteraLVDSSERDESchannelasareceiveroratransmitterforasingledifferentialI/O.Therefore,ann-channelLVDSinterfacecontainsn-serdes_dpablocks.TheI/OPLLsdrivetheLVDSclocktree,providingclockingsignalstotheAlteraLVDSSERDESchannelintheI/Obank.
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FPGAFabricug_altera_lvds2014.08.18Serializer+-tx_inDOUTFigure1:DINAlteraLVDSSERDESChannelDiagram10FunctionalDescriptiontx_out3tx_coreclock3lvds_loadenlvds_fclktx_coreclockLVDSTransmitterLVDSReceiverrx_out10DeserializerDOUTDINBitslipDOUTDINDPAFIFODOUTDINDPACircuitryRetimedDataDIN+-rx_inDPAClock2loadenfclkrx_divfwdclkrx_coreclock3lvds_loadenlvds_fclkrx_coreclockfclklvds_fclkdpa_fclk3dpa_loadendpa_fclkrx_divfwdclkClockMultiplexer8SerialLVDSClockPhasesrx_inclock/tx_inclockLVDSClockDomainDPAClockDomainIOPLL(LocalClockGenerator)EachAlteraLVDSSERDESchannelcanbebrokendownintothefollowingpaths,withsevenfunctionalunits:
Path
Block
Modes
ClockDomain
TXDataPathSerializerTXmodeLVDS
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TXDAT[7:0]FCLKLOADENLVDSOUT476543210SerializerabcdefghABCDEFGHXXXXXXXXug_altera_lvds2014.08.18PathBlockModesClockDomainDPAXXXXXXXXXX765432DPA10aCircuitrybcdefghABCDFIFOEFandSoft-DPACDRmodesDPAFIFOBitslipandDeserializerLocalClockGeneratorSERDESClockMultiplexersDPA-FIFOmodeLVDS-DPAdomaincrossingNon-DPAandDPA-LVDSFIFOmodesSoftCDRmodesSoft-CDRmodeAllmodesDPAclockdomainGeneratesPCLKandLOADENinthesemodesSelectsLVDSclocksourcesforallmodesThiswaveformisspecifictoserializationfactor=8.RXDataPathClockGenerationandMultiplexersSerializer
Theserializerconsistsoftwosetsofregisters.ThefirstsetofregisterscapturestheparalleldatafromthecoreusingtheLVDSfastclock.TheloadenclockisprovidedalongsidetheLVDSfastclock,toenablethesecaptureregistersoncepercoreclockperiod.Afterthedataiscaptured,thedataisthenloadedintoashiftregister,whichshiftstheLSBtowardstheMSB,onebitperfastclockcycle.TheMSBoftheshiftregisterfeedstheLVDSoutputbuffer;hence,higherorderbitsprecedelowerorderbitsintheoutputbitstream.Thefollowingfigureshowstheserializerwaveform.Figure2:LVDSx8SerializerWaveform
Signal
txdat[7:0]fclkloadenlvdsout
Description
Datatobeserialized(supportedserializationfactorsare3-10).Clockusedfortransmitter.Enablesignalforserialization.
LVDSdatastream,outputfromtheAlteraLVDSSERDESchannel.
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RX_IN76543210abcdefghABCDEFGHXXXXXXXXFCLKug_altera_lvds2014.08.18DPAFIFO5
LOADENDPARX_OUT[7:0]FIFOInDPA-FIFOmode,theDPAFIFOsynchronizestheretimeddatatothehigh-speedLVDSclockdomain.XXXXXXXX76543210abcdefghABCDEFGHBecausetheDPAclockmayshiftphaseduringtheinitiallockperiod,theFIFOmustbeheldinresetstateuntiltheDPAlocks;otherwise,theremaybeadatarun-throughconditionduetotheFIFOwritepointercreepinguptothereadpointer.Bitslip
Usebitslipcircuitrytoinsertlatenciesinincrementsofonefclkcyclefordatawordalignment.Thedataslipsonebitforeverypulseoftherx_bitslip_ctrlsignal.Youmustwaitatleastfivecoreclockcyclesbeforecheckingifthedataisalignedbecauseitwilltakeatleasttwocoreclockcyclestopurgetheundefineddata.
Whenenoughbitslipsignalsaresenttorolloverthebitslipcounter,therx_bitslip_maxstatussignalisassertedafterfivecoreclockcyclestoindicatethatithasreacheditsmaximumcountervalueofthebitslipcounterrolloverpoint.
Deserializer
Thedeserializerconsistsofshiftregisters.Thedeserializationfactordeterminesthedepthoftheshiftregisters.Theloadensignalisapulsewithafrequencyofthefclkdividedbythedeserializationfactor.The
deserializerconvertsa1-bitserialdatastreamintoaparalleldatastreambasedonthedeserializationfactor.Figure3:LVDSx8DeserializerWaveform
Signal
rx_infclkloadenrx_out[7:0]
Description
LVDSdatastream,inputtotheAlteraLVDSSERDESchannel.Clockusedforreceiver.Enablesignalfordeserialization.Deserializeddata.
InitializationandReset
Thissectiondescribestheinitializationandresetaspects,usingcontrolcharacters.ThissectionalsoprovidesarecommendedinitializationandresetflowfortheAlteraLVDSSERDESIPcore.
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