ug - altera - lvds(4)

16ClockResourceSummaryTab

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ParameterValueDescriptionActualtx_outclockphaseshift(degrees)

LegalvaluesareSpecifiestheclosestachievabletx_outclockphasedependentontheshifttothedesiredtx_outclockphaseshift.fclkandtx_outclock

frequencies.RefertoSettingtheTransmitterOutputClockParametersonpage17.Legalvaluesaredependentontheserializationfactor.

Allowsyoutospecifytheratioofthefastclockfrequencytotheoutclockfrequency(forexample,themaximumnumberofserialtransitionsperoutclockcycle).

Tx_outclockdivisionfactor

ClockResourceSummaryTab

Thistabintheparametereditorlistsoutalltherequiredfrequencies,phaseshifts,anddutycyclesoftherequiredclocks,includinginstructionsontherequiredconnections.ThistabalsoshowshowtoconfigureandconnectanexternalPLL.

SettingtheReceiverInputClockParameters

Whenusingnon-DPAmode,ifyouwanttheSERDESreceivertosamplethesourcesynchronousdata,youmustspecifytheinclockrelationshiptotherx_indata.Todoso,typeavalueintheDesiredreceiverinclockphaseshift(degrees)parameter.Legalvaluesareevenlydivisibleby45.Ifyouenteranillegalvalue,theactualphaseshiftwillappearinActualreceiverinclockphaseshift(degrees).

Forrisinginclockedgealignedinterfacestotherx_indata(Figure4),select0°asthedesiredreceiverclockphaseshift.ThePLLwillbesetwiththerequiredphaseshiftonfclktocenteritattheSERDESreceiver.Figure4:0°EdgeAlignedinclockx8DeserializerWaveformWithSingleRateClock

Thephaseshiftyouspecifywillberelativetothefclkwhichoperatesattheserialdatarate.Phaseshiftvaluesbetween0°and360°areusedtospecifytherisingedgeoftheinclockwithinasinglebitperiod.Themaximumphaseshiftvalueisdeterminedbythefollowingequation:(Numberoffclkperiodsperinclockperiodx360)-1

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SettingtheTransmitterOutputClockParameters17

Specifyingphaseshiftvaluesgreaterthan360°willchangetheMSBlocationwithintheparalleldata.Note:Bydefault,theMSBfromtheserialdatawillnotbetheMSBontheparalleldata.Youcanusebitslip

tosettheproperwordboundaryontheparalleldata.RefertoAligningtheWordBoundariesformoredetails.Tospecifyacenteralignedinclocktorx_inrelationship(Figure5),enteraphaseshiftvalueof180°fortheDesiredreceiverinclockphaseshift(degrees)parameter.

Figure5:180°CenterAlignedinclockx8DeserializerWaveformWithSingleRateClock

Thephaseshiftvalueyouentertospecifytheinclocktorx_inrelationshipisindependentoftheinclockfrequency.TospecifyacenteralignedDDRinclocktorx_inrelationship(Figure6),enteraphaseshiftvalueof180°fortheDesiredreceiverinclockphaseshift(degrees)parameter.Figure6:180°CenterAlignedinclockx8DeserializerWaveformWithDDRClock

SettingtheTransmitterOutputClockParameters

Thetx_outclockrelationshiptothetx_outdataisspecifiedwithtwoparameters:?Desiredtx_outclockphaseshift(degrees)?Tx_outclockdivisionfactor

Theseparameterssetthephaseandfrequencyofthetx_outclockbasedonthefclkwhichoperatesattheserialdatarate.Youcanspecifythedesiredtx_outclockphaseshiftrelativetothetx_outdataat45°incrementsofthefclk.Youcansetthetx_outclockfrequencyusingtheavailabledivisionfactorsfromthedrop-downlist.

Use0°tospecifythetx_outclockphasetoberisingedgealignedtotheMSBoftheserialdataontx_out(Figure7).

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18SettingtheTransmitterOutputClockParameters

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Figure7:0°EdgeAlignedtx_outclockx8SerializerWaveformwithDivisionFactorof8

Use180°tospecifythetx_outclockphasetocenteralignedtotheMSBoftheserialdataontx_out (Figure8).

Figure8:180°CenterAlignedtx_outclockx8SerializerWaveformwithDivisionFactorof8

Phaseshiftvaluesof0°through315°willpositiontherisingedgeofthetx_outclockwithintheMSBofthetx_outdata.Phaseshiftvaluesbeginningwith360°willpositiontherisingedgeofthetx_outclockinserialbitsaftertheMSB.Forexample,aphaseshiftof540°willpositiontherisingedgeinthecenterofthebitaftertheMSB(Figure9).

Figure9:540°CenterAlignedtx_outclockx8SerializerWaveformwithDivisionFactorof8

UsetheTx_outclockdivisionfactordrop-downlisttosetthetx_outclockfrequency.Figure10showsax8serializationfactorusinga180°phaseshiftwithatx_outclockdivisionfactorof2(DDRclockanddatarelationship).

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Timing19

Figure10:180°CenterAlignedtx_outclockx8SerializerWaveformwithDivisionFactorof2

Timing

ToproperlyperformtiminganalysisontheAlteraLVDSSERDESIPcoreonArria10devices,theQuartusIIsoftwareversion14.0a10generatestherequiredtimingconstraints.

TimingComponents

Table6:TimingComponents

ThistableliststhetimingcomponentsfortheAlteraLVDSSERDESIPcore.

TimingComponent

Description

SourceSynchronousPaths

Thesourcesynchronouspathsarepathswhereclockanddatasignalsarepassedfromthetransmittingdevicestothereceivingdevices.Forexample:

?FPGA/LVDS/TXtoexternalreceivingdevicetransmittingpath?ExternaltransmittingdevicetoFPGA/non-DPAmode/LVDS/RXreceivingpath

DynamicPhaseAlignmentPaths

TheI/Ocapturepathsinsoft-CDRandDPA-FIFOmodesareregisteredbyaDPAblock,whichdynamicallychoosesthebestphasefromthePLLVCOclockstolatchtheinputdata.

TheinternalFPGApathsarethepathsinsidetheFPGAfabric.ThisincludestheLVDSRXhardwaretocoreregisterspaths,coreregisterstoLVDSTXhardwarepathsandotherscoreregisterstocoreregisterspath.TheTimeQuestTimingAnalyzerreportsthecorrespondingtimingmargins.

InternalFPGAPaths

TimingConstraintsandFiles

ToenableyoutoperformtiminganalysisontheAlteraLVDSSERDESIPcoresuccessfully,theIPcoregeneratesthefollowingtimingfiles,whichyoucanlocateinthedirectory.

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20TimingAnalysis

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Table7:TimingFiles

File

Description

_altera_lvds_core20_140_This.sdcallowstheFittertooptimizetiming.sdcmarginswithtimingdrivencompilation.Also

allowstheTimeQuesttiminganalyzertoanalyzethetimingofyourdesign.

TheIPcoreusesthe.sdcforthefollowingoperations:????

CreatingclocksonPLLinputsCreatinggeneratedclocks

Callingderive_clock_uncertaintyCreatingpropermulti-cycleconstraints

Youcanlocatethisfileinthe.qipgeneratedduringtheIPgeneration.

sdc_util.tcl

This.tclfileisalibraryoffunctionsandproceduresthatthe.sdcuses.

TimingAnalysis

TimingAnalysisatI/O

ThissectiondescribesthetiminganalysisattheI/Ointerfacingexternaldevices.SoftCDRModeandDPA-FIFOModeRX

InsoftCDRandDPA-FIFOmode,thereceivingdataiscaptureddynamicallybytheDPAhardware.Asaresult,theTimeQuestTimingAnalyzerdoesnotperformstatictiminganalysisattheI/O.Non-DPAModeRXandReceiverSkewMargin(RSKM)

Changesinthesystemenvironment,suchastemperature,media(cable,connector,orPCB),andloading,affectthereceiver'ssetupandholdtimes;internalskewaffectsthesamplingabilityofthereceiver.Innon-DPAmode,usereceiverskewmargin(RSKM),receiverchannel-to-channelskew(RCCS),andsamplingwindow(SW)specificationstoanalyzethetimingforhigh-speedsource-synchronousdifferentialsignalsinthereceiverdatapath.ThefollowingequationshowstherelationshipbetweenRSKM,RCCS,andSW.Figure11:RSKM

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