6InitializingtheAlteraLVDSSERDESIPCore
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InitializingtheAlteraLVDSSERDESIPCore
WiththeAlteraLVDSSERDESIPcore,thePLLmustbelockedtothereferenceclockpriortousingtheSERDESblocksfordatatransfer.ThePLLstartstolocktothereferenceclockduringdeviceinitialization.ThePLLisoperationalwhenthePLLachieveslockduringusermode.Iftheclockreferenceisnotstableduringdeviceinitialization,thePLLoutputclockphaseshiftsbecomescorrupted.
WhenthePLLoutputclockphaseshiftsarenotsetcorrectly,thedatatransferbetweenthehigh-speedLVDSdomainandthelow-speedparalleldomainmightnotbesuccessful,whichleadstodatacorruption.Assertthepll_aresetportforatleast10ns,andthendeassertthepll_aresetportandwaituntilthePLLlockbecomesstable.AfterthePLLlockportassertsandisstable,theSERDESblocksarereadyforoperation.WhenusingDPA,furtherstepsarerequiredforinitializationandresetrecovery.TheDPAcircuitsamplestheincomingdataandfindstheoptimalphasetapfromthePLLtocapturedataonareceiverchannel-by-channelbasis.IfthePLLhasnotlockedtoastableclocksource,theDPAcircuitmightlockprematurelytoanon-idealphasetap.Usetherx_dpa_resetporttokeeptheDPAinresetuntilthePLLlocksignalisassertedandstable.
Therx_dpa_lockedsignalassertswhentheDPAhasfoundtheoptimalphasetap.
Note:Alterarecommendsassertingtherx_fifo_resetportaftertherx_dpa_lockedsignalasserts,and
thendeasserttherx_fifo_resetporttobeginreceivingdata.EachtimetheDPAshiftsthephasetapsduringnormaloperationtotrackvariationsbetweentherelationshipofthereferenceclocksourceandthedata,thetimingmarginforthedatatransferbetweenclockdomainsisreduced.
TheAlteraLVDSSERDESIPcoreassertstherx_dpa_lockedportuponinitialDPAlock.WhenyouenabletheEnableDPAlossoflockononechangeoption,therx_dpa_lockedportdeassertsafteronechangeinphase.Ifthisoptionisdisabled,therx_dpa_lockedsignalwilldeassertaftertwophasechangesinthesamedirection.
Note:Alterarecommendsusingthedatacheckerstoensuredataaccuracy.
ResettingtheDPA
Whenthedatabecomescorrupted,youmustresettheDPAcircuitryusingtherx_dpa_resetportandrx_fifo_resetport.
Asserttherx_dpa_resetporttoresettheentireDPAblock.ThisrequirestheDPAtobetrainedbeforeitisreadyfordatacapture.
Note:Alterarecommendstogglingtherx_fifo_resetportafterrx_dpa_lockedisasserted.Thisensures
thesynchronizationFIFOissetwiththeoptimaltimingtotransferdatabetweentheDPAandhigh-speedLVDSclockdomains.Asserttherx_fifo_resetporttoresetonlythesynchronizationFIFO.Thisallowsyoutocontinuesystemoperationwithouthavingtore-traintheDPA.UsingthisportcanfixdatacorruptionbecauseitresetstheFIFO;however,itdoesnotresettheDPAcircuit.
WhentheDPAislocked,theAlteraLVDSSERDESblockisreadytocapturedata.TheDPAfindstheoptimalsamplelocationtocaptureeachbit.Thenextstepistosetupthewordboundaryusingcustomlogictocontroltherx_bitslip_ctrlportonachannel-by-channelbasis.
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AligningtheWordBoundaries7
Thebitslipcircuitcanberesetusingtherx_bitslip_resetport.ThiscircuitcanberesetanytimeandisnotdependentonthePLLorDPAcircuitoperation.
AligningtheWordBoundaries
Toalignthewordboundaries,itisusefultohavecontrolcharactersinthedatastreamsothatyourlogiccanhaveaknownpatterntosearchfor.Youcancomparethedatareceivedforeachchannel,comparetothecontrolcharacteryouarelookingfor,thenpulsetherx_bitslip_ctrlportasrequireduntilyousuccessfullyreceivethecontrolcharacter.
Note:Alterarecommendssettingthebitsliprollovercounttothedeserializationfactororhigher,which
allowsenoughdepthinthebitslipcircuittorollthroughanentirewordifrequired.Ifyoudonothavecontrolcharactersinthereceiveddata,youneedadeterministicrelationshipbetweenthereferenceclockanddatatopredictthewordboundaryusingtimingsimulationorlaboratorymeasure-ments.Thisappliesonlyfornon-DPAmode.TheonlywaytoensureadeterministicrelationshiponthedefaultwordpositionintheSERDESwhenthedevicepowersup,oranytimethePLLisreset,istohaveareferenceclockequaltothedataratedividedbythedeserializationfactor.Forexample,ifthedatarateis800Mbps,andthedeserializationfactoris8,thePLLrequiresa100-MHzreferenceclock.ThisisimportantbecausethePLLlockstotherisingedgeofthereferenceclock.Ifyouhaveonerisingedgeonthereferenceclockperserialwordreceived,thedeserializeralwaysstartsatthesameposition.Usingtimingsimulation,orlabmeasurements,monitortheparallelwordsreceivedanddeterminehowmanypulsesarerequiredontherx_bitslip_ctrlporttosetyourwordboundaries.Youcancreateasimplestatemachinetoapplytherequirednumberofpulseswhenyouenterusermode,oranytimeyouresetthePLL.
Note:WhenusingDPAorsoft-CDRmodes,thewordboundaryisnotdeterministic.Theinitialtraining
oftheDPAallowsittomoveforwardorbackwardinphaserelativetotheincomingserialdata.Thus,therecanbea±1-bitofvarianceintheserialbitwheretheDPAinitiallylocks.Iftherearenotrainingpatternsorcontrolcharactersavailableintheserialbitstreamtouseforwordalignment,Alterarecommendsusingnon-DPAmode.
RecommendedInitializationandResetFlow
AlterarecommendsthatyoufollowthesestepstoinitializeandresettheAlteraLVDSSERDESIPcore:1.Duringentryintousermode,oranytimeinusermodeoperationwhentheinterfacerequiresareset,assertthepll_aresetandrx_dpa_resetports.
2.Deassertthepll_aresetportandmonitorthepll_lockedport.Fornon-DPAmode,skiptostep7.3.Deasserttherx_dpa_resetportafterthepll_lockedportbecomesassertedandstable.
4.ApplytheDPAtrainingpatternandallowtheDPAcircuittolock.(Ifatrainingpatternisnotavailable,anydatawithtransitionsisrequiredtoallowtheDPAtolock.)RefertotherespectivedevicedatasheetforDPAlocktimespecifications.
5.Waitfortherx_dpa_lockedporttoassert.
6.Assertrx_fifo_resetforatleastoneparallelclockcycle,andthende-assertrx_fifo_reset.7.Asserttherx_bitslip_resetportforatleastoneparallelclockcycle,andthendeasserttherx_bitslip_resetport.
8.Beginwordalignmentbyapplyingpulsesasrequiredtotherx_bitslip_ctrlport.
9.Whenthewordboundariesareestablishedoneachchannel,theinterfaceisreadyforoperation.
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8Signals
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Signals
ThefollowingtableslisttheinputandoutputsignalsfortheAlteraLVDSSERDESIPcore.
Note:NrepresentstheLVDSinterfacewidthandthenumberofserialchannelswhileJrepresentsthe
SERDESfactoroftheinterface.
Table2:CommonTXandRXSignals
SignalName
inclockpll_areset
WidthDirectionTypeDescription
111
InputInputOutput
ClockResetControl
PLLreferenceclock.
Active-highasynchronousresettoallblocksinAlteraLVDSSERDESandPLL.AssertedwheninternalPLLislocked.
pll_locked
Table3:RXSignals
SignalName
rx_in
rx_bitslip_reset
WidthDirectionTypeDescription
NNN
InputInputInput
DataResetControl
LVDSserialinputdata.
Asynchronous,active-highresettotheclock-dataalignmentcircuitry(bitslip).
Positive-edgetriggeredincrementforbitslipcircuitry.Eachassertionaddsonebitoflatencytothereceivedbitstream.
Asynchronous,active-highsignalpreventstheDPAcircuitryfromswitchingtoanewclockphaseonthetargetchannel.Whenheldhigh,theselectedchannel(s)holdtheircurrentphasesetting.Whenheldlow,theDPAblockonselectedchannel(s)monitorsthephaseoftheincomingdatastreamcontinuouslyandselectsanewclockphasewhenneeded.ApplicableinDPA-FIFOandsoft-CDRmodesonly.
Asynchronous,active-highresettoDPAblocks.Minimumpulsewidthisoneparallelclockperiod.ApplicableinDPA-FIFOandsoft-CDRmodesonly.
Asynchronous,active-highresettoFIFOblock.Minimumpulsewidthisoneparallelclockperiod.ApplicableinDPA-FIFOmodeonly.
rx_bitslip_ctrl
rx_dpa_hold
NInputControl
rx_dpa_reset
NInputReset
rx_fifo_reset
NInputReset
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Signals9
SignalName
rx_out
WidthDirectionTypeDescription
N*JOutputData
Receiverparalleldataoutput.Synchronoustorx_coreclockin(DPA-FIFOandnon-DPAmodes).Insoft-CDRmode,each
channelhasparalleldatasynchronoustoitsrx_divfwdclk.
Bitsliprolloversignal.Highwhenthenextassertionofrx_bitslip_ctrlresetstheserialbitlatencyto0.
CoreclockforRXinterfacesprovidedbythePLL.NotavailablewhenusinganexternalPLL.
Theperchannel,dividedclockwiththeidealDPAphase.Therecoveredslowclockforagivenchannel.Applicableinsoft-CDRmodeonly.Becauseeachchannelmayhaveadifferentidealsamplingphase,therx_divfwdclksmaynotbeedge-alignedwitheachother.Eachrx_divfwdclkmustdrivethecorelogicwithdatafromthesamechannel.
AssertedwhentheDPAblockselectstheidealphase.TheAlteraLVDSSERDESIPcoredrivestherx_dpa_lockedport.TheDPAlogicassertstherx_dpa_lockedsignalwhenthesignalsettlesonanidealphaseforthatgivenchannel.Therx_dpa_lockedportwillde-assertiftheDPAmovestwophasesinthesamedirectionoriftheDPAmovesonephase.Therx_dpa_lockedsignalwillstilltogglewhentherx_dpa_holdsignalis
asserted,andshouldbeignoredbyuserlogicwhentherx_dpa_holdsignalisasserted.ApplicableinDPA-FIFOandsoft-CDRmodesonly.
rx_bitslip_max
NOutputControl
rx_coreclock
1OutputClock
rx_divfwdclk
NOutputClock
rx_dpa_locked
NOutputControl
Table4:TXSignals
SignalName
tx_intx_outtx_outclock
WidthDirectionTypeDescription
N*JN1
InputOutputOutput
DataDataClock
Paralleldatafromthecore.LVDSserialoutputdata.
Externalreferenceclock(sentoffchipviatheTXdatapath).Source-synchronouswithtx_out.
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SignalName
tx_coreclock
WidthDirectionTypeDescription
1OutputClock
Theclockthatdrivesthecorelogicfeedingtheserializer.NotavailableintheexternalPLLmode.
Table5:ExternalPLLSignals
Forinstructionsonsettingthefrequencies,dutycycles,andphaseshiftsoftherequiredPLLclocksforexternalPLLmode,refertotheClockResourceSummarytabintheIPParameterEditor.
SignalName
ext_fclk
WidthDirectionTypeDescription
1InputClock
LVDSfastclock.Usedforserialdatatransfer.Requiredinallmodes.Youmustconnectthissignaltothelvds_clk[0]portofthePLL.Thissignalisconfiguredasoutclock[0]fromthePLL.UseEnableaccesstoPLLLVDS_CLK/LOADENoutputportintheIOPLLgeneration.
LVDSloadenable.Usedforparallelload.NotrequiredinRXSoft-CDRmode.Youmustconnectthissignaltotheloaden[0]portofthePLL.Thissignalisconfiguredas
outclock[1]fromthePLL.UseEnableaccesstoPLLLVDS_CLK/LOADENoutputportintheIOPLLgeneration.
Theclockthatdrivesthecorelogicfeedingtheserializer(TX)/receivingfromthedeserializer(RX).ThissignalisstillpresentinRXsoft-CDRmode,eventhoughtheRXcoreregistersareclockedusingtherx_divfwdclk.RequiredforRXDPA-FIFOandRXSoft-CDRmodesonly.ProvidestheVCOclockstotheDPAcircuitryforoptimalphaseselection.Youmustconnectthissignaltothephout[7:0]signalfromthePLL.UseEnableaccesstoPLLDPAoutputportinIOPLLgeneration.PLLlocksignal.RequiredforRXDPA-FIFOandRXSoft-CDRmodesonly.
Phase-shiftedversionoffastclockrequiredforTXoutclockphaseshiftsthatarenotmultiplesof180degrees.
Phase-shiftedversionofloadenrequiredforTXoutclockphaseshiftsthatarenotmultiplesof180degrees.
ext_loaden
1InputClock
ext_coreclock
1InputClock
ext_vcoph[7:0]
InputClock
ext_pll_locked
11
InputInput
DataClock
ext_tx_outclock_fclk
ext_tx_outclock_loaden
1InputClock
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