ug_altera_lvds2014.08.18
ParameterSettings11
ParameterSettings
YoucanparameterizetheAlteraLVDSSERDESIPcoreusingtheIPParameterEditor.
GeneralSettingsTab
Parameter
Value
Description
Functionalmode
????TX
RXNon-DPARXDPA-FIFORXSoft-CDR
Specifiesthefunctionalmodeoftheinterface.
Numberofchannels
?1to72forTXSpecifiesthenumberofserialchannelsinthe?1to24forRXNon-interface.DPA?Decrementonechannelforthededicated?1to24forRXDPA-referenceclockpin(refclk)forTX,RX
FIFONon-DPA,andRXDPA.Notusingthe?1to12forRXSoft-dedicatedreferenceclockpinmay
CDRcontributetohigherjitter.
?DecreasebyonechannelfortheTXoutclockpin(tx_outclock)ifused.
150.0to1600.0
Specifiesthedatarate(inMbps)ofasingleserialchannel.ThevalueisdependentontheFunctionalmodeparametersettings.
Datarate
SERDESfactorUseclock-pindrive
3,4,5,6,7,8,9,and10Specifiestheserializationrateordeserializa-tionratefortheLVDSinterface.
Whenenabled,theIPcorebypassesthePLLandtheinterfaceisdrivenwithaclockpin.
—
Note:Thisfeatureisnotsupportedin
thecurrentversionoftheQuartusIIsoftware.Whenenabled,theIPcoreuseslegacytop-levelnamesthatarecompatiblewith
ALTLVDS_TXandALTLVDS_RXIPcores.
Usebackwards-compatibleportnames
—
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12PLLSettingsTab
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PLLSettingsTab
Parameter
Value
Description
UseexternalPLL
—
Whenenabled,theIPcoredoesnotinstantiateaPLLlocally.Instead,aseriesofclockconnectionsareelaboratedwiththeprefix\thatshouldbeconnectedtoanexternallygeneratedPLL.ThisoptionallowsyoutoaccessalloftheavailableclocksfromthePLL,aswellasuseadvancedPLLfeaturessuchasclockswitchover,bandwidthpresets,dynamicphasestepping,anddynamicreconfiguration.
TheClockResourceSummarytabguidesyoutoconfigureyourexternalPLL.
DesiredinclockfrequencyActualinclockfrequencyFPGA/PLLspeedgradeEnablepll_aresetport
————
SpecifiestheinclockfrequencyinMHzSpecifiestheclosestinclockfrequencytothedesiredfrequencythatcansourcetheinterface.SpecifiestheFPGA/PLLspeedgradewhichdeterminestheoperationrangeofthePLL.Whenenabled,thisparameterexposesthepll_aresetport,whichyoucanusetoresettheentireLVDSinterface.
SpecifieswhichclocknetworktheAlteraLVDSSERDESIPcoreshouldexportaninternallygeneratedcoreclockonto.
Note:Thisfeatureisnotsupportedinthe
currentversionoftheQuartusIIsoftware.However,thiscanbemanuallyaddedusingQSFassignments.
Coreclockresourcetype—
ReceiverSettingsTab
Parameter
Value
Description
BitslipSettingsEnablebitslipmode
—
Whenenabled,thisparameteraddsabitslipblocktothedatapathofthereceiverandexposestherx_bitslip_ctrlport(oneinputperchannel).Everyassertionoftherx_bitslip_ctrlsignaladdsonebitofseriallatencytothedatapathofthespecifiedchannel.
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ReceiverSettingsTab13
ParameterValueDescription
Enablerx_bitslip_resetport—
Whenenabled,thisparameterexposestherx_bitslip_resetport(oneinputperchannel),whichyoucanusetoresetthebitslip.
Whenenabled,thisparameterexposestherx_bitslip_maxport(oneoutputperchannel).Whenasserted,thenextrisingedgeofrx_bitslip_ctrlresetsthelatencyofthebitsliptozero.
Enablerx_bitslip_maxport—
Bitsliprollovervalue
3,4,5,6,7,8,9,Setsthemaximumlatencythatcanbeinjectedusing
10,11bitslip.Whenitreachesthatvalue,itrollsoverand
therx_bitslip_maxsignalisasserted.Thedefaultvalueis10.
Note:Alterarecommendssettingthis
parametertoavalueequaltoorgreaterthanthedeserializationfactor.
DPASettings
Enablerx_dpa_resetport
—
Whenenabled,theIPcoreexposestherx_dpa_reset port,whichyoucanusetoresettheDPAlogicofeachchannelindependently.Formerlyknownasrx_reset.
Whenenabled,userlogicdrivestherx_fifo_resetportwhichyoucanusetoresettheDPA-FIFOblock.
Whenenabled,theIPcoreexposestherx_dpa_holdinputport(oneinputperchannel).Whensethigh,theDPAlogicinthecorrespondingchanneldoesnotswitchsamplingphases.Therx_dpa_holdportisformerlyknownasrx_dpll_holdport.
Enablerx_fifo_resetport—
Enablerx_dpa_holdport—
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14ReceiverSettingsTab
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ParameterValueDescription
EnableDPAlossoflockononechange
—
Whenenabled,theAlteraLVDSSERDESIPcoredrivestherx_dpa_lockedsignallowwhentheDPAchangesphaseselectionfromtheinitiallylockedposition.TheAlteraLVDSSERDESIPcoredrivestherx_dpa_lockedsignalhighiftheDPAchangesthephaseselectionbacktotheinitiallockedposition.
Whendisabled,theAlteraLVDSSERDESIPcoredrivestherx_dpa_lockedsignallowwhentheDPAmovestwophasesinthesamedirectionawayfromtheinitiallockedposition.TheAlteraLVDS
SERDESIPcoredrivestherx_dpa_locked signalhighiftheDPAchangesthephaseselectiontobewithinonephaseorsamephaseastheinitiallockedposition.
Ade-assertionofrx_dpa_lockeddoesnotindicatethedataisinvalid,itindicatestheDPAhaschangedphasetapstotrackvariationsbetweentheinclockandrx_indata.Alterarecommendsusingdatacheckerstoverifydataaccuracy.
EnableDPAalignmentonlytorisingedgesofdata
—
Whenenabled,DPAlogiccountstherisingedgesontheincomingserialdataonly.Whendisabled,DPAlogiccountstherisingandfallingedges.Note:Thisportisonlyrecommendedforuse
inhighjittersystems,andAlterarecommendsdisablingthisportintypicalapplications.
(Simulationonly)SpecifyPPMdriftontherecoveredclock(s)
—
SpecifiestheamountofphasedrifttheALTERA_LVDSsimulationmodelshouldaddtotherecoveredrx_divfwdclks.
Note:Thisfeatureisnotsupportedinthe
currentversionoftheQuartusIIsoftware.
Non-DPASettings
Desiredreceiverinclockphaseshift(degrees):
—
SpecifiestheidealphasedelayoftheinclockwithrespecttotransitionsintheincomingserialdataindegreesoftheLVDSfastclock.Forexample,
specifying180degreesimpliestheinclockiscenteralignedwiththeincomingdata.
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TransmitterSettingsTab15
ParameterValueDescription
ActualreceiverinclockphaseshiftLegalvaluesareSpecifiestheclosestachievablereceiverinclock(degrees)dependentonthephaseshifttothedesiredreceiverinclockphase
fclkandinclockshift.frequencies.RefertoSettingtheReceiverInputClockParametersonpage16.
TransmitterSettingsTab
Parameter
Value
Description
TXcoreregistersclock
Allowsyoutoeitherclockthecoreregisterswiththetx_coreclockorthePLLrefclk.Ifyouselect
tx_coreclockorinclock,therefclkfrequencymustbeequaltothe
dataratedividedbytheserializationfactor.inclock
ThisparameterisavailableinTXfunctionalmodeonly.
—
Whenenabled,theIPcoreexposesthetx_
coreclockportwhichyoucanusetodrivethecorelogicfeedingthetransmitter.
Whenenabled,theIPcoreexposesthetx_
outclockport.Thefrequencyofthetx_outclockportisdependentonthesettingforthetx_outclockdivisionfactorparameter.Thephaseofthetx_outclockportisdependentontheDesiredtx_outclockphaseshiftparameter.Thisparametertakesupanadditionalchannel,whichreducesthemaxnumberofchannelsperTXinterfaceby1AllowsyoutospecifythephaserelationshipbetweentheoutclockandoutgoingserialdataindegreesoftheLVDSfastclock.
Enabletx_coreclockport
Enabletx_outclockport
—
Desiredtx_outclockphaseshift(degrees)
RefertotheSettingtheTransmitterOutputClockParametersonpage17.
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