陕西理工学院毕业论文（设计）
参考文献
[1]李焱.基于DDS控制技术下的型号发生器的设计与实现 .吉林：吉林大学出版社， 2007.9. [2]施羽暇，吕威.基于DDS技术的正弦信号发生器设计.信息技术，2007. [3]汪伟，王元中.基于FPGA的DDS的设计与实现.山西电子技术，2007. [4]王建和.采用DDS技术实现的频率合成信号发生器.电子技术，1997.
[5]潘志良.基于FPGA的DDS信号源的设：[硕士学位论文].武汉：武汉理工大学通信与信息系统专
业，2007.4.
[6]郭立浩.基于即FPGA的直接数字频率合成器的研究与应用:[硕士学位论文」.西安:西北工业大学
电路与系统专业，2006.
[7]H.T.Nicholas III H.Samulei.An analysis of the output spectrum of Direct Digital
Frequency Synthesizers in the presence of phase accumulator truncation,IEEE Proc.41st AFCS,1999:495～502
[8]Vankka J.Spur reduction techniques in sine out-put direct digital
synthesis,IEEE Proc.50th AFCS,2001:951～959
[9]余勇，郑小林．基于FPGA的DDS正弦信号发生器的设计和实现[J]．电子器件，2005(9)：596-599． [10]郭军朝，王森章．一种高速低功耗直接数字频率合成器的设计与实现[J]．微电子学，2004，10(5)：572—574．
[11]吉训生．一种高效实用的直接数字频率合成器的设计和实现[J]．现代电子技术，2003，15：99—101．
[12]傅玉朋，李明浩，吕进华．DDS技术的FPGA设计与实现[J]．大连民族学院学报，2004(3)：4647．
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陕西理工学院毕业论文（设计）
附录A 英文资料及翻译
Fundamentals of DDS Technology
Overview
Direct digital synthesis (DDS) is a technique for using digital data processing blocks as a means to generate a frequency- and phase-tunable output signal referenced to a fixed-frequency precision clock source. In essence, the reference clock frequency is “divided down” in a DDS architecture by the scaling factor set forth in a programmable binary tuning word. The tuning word is typically 24-48 bits long which enables a DDS implementation to provide superior output frequency tuning resolution.
Today’s cost-competitive, high-performance, functionally-integrated, and small package-sized DDS products are fast becoming an alternative to traditional frequency-agile analog synthesizer solutions. The integration of a high-speed, high-performance, D/A converter and DDS architecture onto a single chip (forming what is commonly known as a Complete-DDS solution) enabled this technology to target a wider range of applications and provide, in many cases, an attractive alternative to analog-based PLL synthesizers. For many applications, the DDS solution holds some distinct advantages over the equivalent agile analog frequency synthesizer employing PLL circuitry.
DDS advantages: · Micro-Hertz tuning resolution of the output frequency and sub-degree phase tuning capability, all under complete digital control. · Extremely fast “hopping speed” in tuning output frequency (or phase), phase-continuous frequency hops with no over/undershoot or analog-related loop settling time anomalies. · The DDS digital architecture eliminates the need for the manual system tuning and tweaking associated with component aging and temperature drift in analog synthesizer solutions. · The digital control interface of the DDS architecture facilitates an environment where systems can be remotely controlled, and minutely optimized, under processor control. · When utilized as a quadrature synthesizer, DDS afford unparalleled matching and control of I and Q synthesized outputs.
Theory of Operation
In its simplest form, a direct digital synthesizer can be implemented from a precision reference clock, an address counter, a programmable read only memory (PROM), and a D/A converter (see Figure A-1).
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陕西理工学院毕业论文（设计）
Figure A-1. Simple Direct Digital Synthesizer
In this case, the digital amplitude information that corresponds to a complete cycle of a sinewave is stored in the PROM. The PROM is therefore functioning as a sine lookup table. The address counter steps through and accesses each of the PROM’s memory locations and the contents (the equivalent sine amplitude words) are presented to a high-speed D/A converter. The D/A converter generates an analog sinewave in response to the digital input words from the PROM. The output frequency of this DDS implementation is dependent on 1.) the frequency of the reference clock, and 2.) the sinewave step size that is programmed into the PROM. While the analog output fidelity, jitter, and AC performance of this simplistic architecture can be quite good, it lacks tuning flexibility. The output frequency can only be changed by changing the frequency of the reference clock or by reprogramming the PROM. Neither of these options support high-speed output frequency hopping.
Figure A-2. Frequency-tunable DDS System
With the introduction of a phase accumulator function into the digital signal chain, this
architecture becomes a numerically-controlled oscillator which is the core of a highly-flexible
DDS device. As figure A-2 shows, an N-bit variable-modulus counter and phase register are implemented in the circuit before the sine lookup table, as a replacement for theaddress counter. The carry function allows this function as a “phase wheel” in the DDS architecture. To understand this basic function, visualize the sinewave oscillation as a vector rotating around a phase circle (see Figure A-3). Each designated point on the phase wheel corresponds to the equivalent point on a cycle of a sine waveform. As the vector rotates around the wheel, visualize that a corresponding output sinewave is being generated. One revolution of the vector around the phase wheel, at a constant speed, results in one complete cycle of the output sinewave. The
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陕西理工学院毕业论文（设计）
phase accumulator is utilized to provide the equivalent of the vector’s linear rotation around the phase wheel. The contents of the phase accumulator correspond to the points on the cycle of the output sinewave.
Figure A-3. Digital Phase Wheel
The number of discrete phase points contained in the “wheel” is determined by the resolution, N, of the phase accumulator. The output of the phase accumulator is linear and cannot directly be used to generate a sinewave or any other waveform except a ramp. Therefore, a phase-toamplitude lookup table is used to convert a truncated version of the phase accumulator’s instantaneous output value into the sinewave amplitude information that is presented to the D/A converter. Most DDS architectures exploit the symmetrical nature of a sinewave and utilize mapping logic to synthesize a complete sinewave cycle from ? cycle of data from the phase accumulator. The phase-to-amplitude lookup table generates all the necessary data by reading forward then back through the lookup table.
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陕西理工学院毕业论文（设计）
Figure A-4. Signal flow through the DDS architecture
The phase accumulator is actually a modulus M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by a digital word M contained in a “delta phase register” that is summed with the overflow of the counter. The word in the delta phase register forms the phase step size between reference clock updates; it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and completes its equivalent of a sinewave cycle. For a N=32-bit phase accumulator, an M value of 0000…0001(one) would result in the phase accumulator overflowing after 232 reference clock cycles (increments). If the M value is changed to 0111…1111, the phase accumulator will overflow after only 21clock cycles, or two reference clock cycles. This control of the jump size constitutes the frequency tuning rThe relationship of the phase accumulator and delta phase accumulator form the basic tuning equation for DDS architecture:
FOUT = (M (REFCLK)) /2n
Where: FOUT = the output frequency of the DDS M = the binary tuning word
REFCLK = the internal reference clock frequency (system clock) N = The length in bits of the phase accumulator
Changes to the value of M in the DDS architecture result in immediate and phase-continuous
changes in the output frequency. In practical application, the M value, or frequency tuning word,is loaded into an internal serial or byte-loaded register which precedes the parallel-output delta phase register. This is generally done to minimize the package pin count of the DDS device.Once the buffer register is loaded, the parallel-output delta phase register is clocked and the DDS output frequency changes. Generally, the only speed limitation to changing the output frequency of a DDS is the maximum rate at which the buffer register
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