陕西理工学院毕业论文（设计）
inclock :IN STD_LOGIC;
q :OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT MUX41A
PORT(A:IN STD_LOGIC_VECTOR(9 DOWNTO 0); B:IN STD_LOGIC_VECTOR(9 DOWNTO 0); C:IN STD_LOGIC_VECTOR(9 DOWNTO 0); SS:IN STD_LOGIC_VECTOR(1 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT;
SIGNAL F32B :STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL D32B :STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL DIN32B:STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL P10B :STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL LIN10B:STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL SIN10B:STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL SIND:STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL SD:STD_LOGIC_VECTOR( 9 DOWNTO 0); SIGNAL JD:STD_LOGIC_VECTOR( 9 DOWNTO 0); BEGIN
F32B(27 DOWNTO 20)<=FWORD;F32B(31 DOWNTO 28)<=\ P10B(1 DOWNTO 0)<=\
F32B(19 DOWNTO 0)<=\
u1:ADDER32B PORT MAP(A=>F32B,B=>D32B,S=>DIN32B); u2:REG32B PORT MAP (DOUT=>D32B,DIN=>DIN32B,LOAD=>CLK); u3:SIN_ROM PORT MAP(address=>SIN10B,q=>SIND,inclock=>CLK); u4:S_ROM PORT MAP(address=>SIN10B,q=>SD,inclock=>CLK); u5:J_ROM PORT MAP(address=>SIN10B,q=>JD,inclock=>CLK);
u6:ADDER10B PORT MAP(A=>P10B,B=>D32B(31 DOWNTO 22),S=>LIN10B); u7:REG10B PORT MAP(DOUT=>SIN10B,DIN=>LIN10B,LOAD=>CLK); u8:MUX41A PORT MAP(SS=>SC,S=>FOUT,A=>SIND,B=>SD,C=>JD); END;
第 36 页 共 36 页