COMPONENT dff1 port(clr:in std_logic;
en:in std_logic_vector(2 downto 0);-----使能信号 clk:in std_logic;
d1:in std_logic_vector(3 downto 0);------输入信号 q1:out std_logic_vector(3 downto 0)); end COMPONENT;
COMPONENT dff2 port(clr:in std_logic;
en:in std_logic_vector(2 downto 0);-----使能信号 clk:in std_logic;
d2:in std_logic_vector(3 downto 0);------输入信号 q2:out std_logic_vector(3 downto 0)); end COMPONENT;
COMPONENT dff3 port(clr:in std_logic;
en:in std_logic_vector(2 downto 0);-----使能信号 clk:in std_logic;
d3:in std_logic_vector(3 downto 0);------输入信号 q3:out std_logic_vector(3 downto 0)); end COMPONENT;
COMPONENT dff4 port(clr:in std_logic;
en:in std_logic_vector(2 downto 0);-----使能信号 clk:in std_logic;
d4:in std_logic_vector(3 downto 0);------输入信号
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q4:out std_logic_vector(3 downto 0)); end COMPONENT;
COMPONENT REPLAY port(clr:in std_logic; rsh:in std_logic;
pn:buffer std_logic_vector(2 downto 0)); ---使能输出 end COMPONENT;
COMPONENT select1
PORT( pn:in std_logic_vector(2 downto 0);
din0,din1,din2,din3:in std_logic_vector(3 downto 0);
q00,q01,q02,q03,q10,q11,q12,q13,q20,q21,q22,q23,q30,q31,q32,q33:in std_logic_vector(3 downto 0);
dout0,dout1,dout2,dout3:out STD_LOGIC_VECTOR(3 DOWNTO 0)); end COMPONENT;
COMPONENT shumaguan IS PORT(
DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); led:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); end COMPONENT;
SIGNAL CLK_IN,CLK_OUT:std_logic; signal count1,count2,count3,count4:std_logic;
signal tdin0,tdin1,tdin2,tdin3,tdout0,tdout1,tdout2,tdout3:std_logic_vector(3 downto 0); signal
q10,q11,q12,q13,q20,q21,q22,q23,q30,q31,q32,q33,q40,q41,q42,q43:std_logic_vector(3 downto 0);
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signal tled0,tled1,tled2,tled3:std_logic_vector(6 downto 0); signal tsel:std_logic_vector(1 downto 0); signal ten,tpn:std_logic_vector(2 downto 0); begin
U0:fenpinl port map(clk,clk_out);
U1:count10 port map(clr,clk_out,tdin0,count1);----十毫秒 U2:count10 port map(clr,count1,tdin1,count2);-----百毫秒 U3:count10 port map(clr,count2,tdin2,count3);-----个位秒 U4:count10 port map(clr,count3,tdin3,count4);-----十位秒 U5:RECORD1 port map(clr,rst,ten); U6:dff1 port map(clr,ten,clk,tdin0,q10); U7:dff1 port map(clr,ten,clk,tdin1,q11); U8:dff1 port map(clr,ten,clk,tdin2,q12); U9:dff1 port map(clr,ten,clk,tdin3,q13); U10:dff2 port map(clr,ten,clk,tdin0,q20); U11:dff2 port map(clr,ten,clk,tdin1,q21); U12:dff2 port map(clr,ten,clk,tdin2,q22); U13:dff2 port map(clr,ten,clk,tdin3,q23); U14:dff3 port map(clr,ten,clk,tdin0,q30); U15:dff3 port map(clr,ten,clk,tdin1,q31); U16:dff3 port map(clr,ten,clk,tdin2,q32); U17:dff3 port map(clr,ten,clk,tdin3,q33); U18:dff4 port map(clr,ten,clk,tdin0,q40); U19:dff4 port map(clr,ten,clk,tdin1,q41); U20:dff4 port map(clr,ten,clk,tdin2,q42); U21:dff4 port map(clr,ten,clk,tdin3,q43); U22:REPLAY port map(clr,rsh,tpn); U23:SELECT1
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port
map(tpn,tdin0,tdin1,tdin2,tdin3,q10,q11,q12,q13,q20,q21,q22,q23,q30,q31,q32,q33,q40,q41,q42,q43,tdout0,tdout1,tdout2,tdout3); U24:shumaguan port map(tdout0,tled0); U25:shumaguan port map(tdout1,tled1); U26:shumaguan port map(tdout2,tled2); U27:shumaguan port map(tdout3,tled3);
led0<=tled0;led1<=tled1;led2<=tled2;led3<=tled3;
end behave;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fenpinl IS --------分频器 PORT(CLK_IN:IN STD_LOGIC; CLK_OUT:OUT STD_LOGIC); END ENTITY fenpinl;
ARCHITECTURE structure of fenpinl is constant count0:integer:=500000; begin
divide_clk:process(CLK_IN) variable n0:integer range 0 to 499999; begin
IF RISING_EDGE(CLK_IN) THEN if(n0<(count0/2))then CLK_OUT<='0'; n0:=n0+1;
elsif(n0 23 CLK_OUT<='1'; n0:=n0+1; else n0:=0; END if; END IF; END PROCESS divide_clk; END ARCHITECTURE structure; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count10 is ----------十进制计数器 port(clk,clr:in std_logic;----时钟/清零信号 dout:buffer std_logic_vector(3 downto 0); co:out std_logic);-------输出/进位信号 end count10; architecture behave of count10 is begin process(clr,clk) begin if clr='0' then dout<=\ elsif(rising_edge(clk)) then if dout=\ co<='1'; else dout<=dout+1;co<='0'; end if; end if; end process; 24