LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY select1 IS ------------------选择模块 PORT( pn:in std_logic_vector(2 downto 0);
din0,din1,din2,din3:in std_logic_vector(3 downto 0);
q00,q01,q02,q03,q10,q11,q12,q13,q20,q21,q22,q23,q30,q31,q32,q33:in std_logic_vector(3 downto 0);
dout0,dout1,dout2,dout3:out STD_LOGIC_VECTOR(3 DOWNTO 0)); end;
architecture behave of select1 is begin
process(pn,din0,din1,din2,din3,q00,q01,q02,q03,q10,q11,q12,q13,q20,q21,q22,q23,q30,q31,q32,q33) begin case pn is
when \when \when \when \when \when others => dout0<=q30;dout1<=q31;dout2<=q32;dout3<=q33; end case; end process; end;
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY shumaguan IS PORT(
DIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); led:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END shumaguan;
ARCHITECTURE ART OF shumaguan IS BEGIN
PROCESS(DIN) BEGIN CASE DIN IS
WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \
--0 --1 --2 --3 --4 --5
WHEN \ --6 WHEN \ WHEN \ WHEN \ WHEN OTHERS=>led<=\ END CASE; END PROCESS;
END ARCHITECTURE ART;
--7 --8 --9
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