end behave;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity RECORD1 is --------记录模块 port( clr:in std_logic; RST:in STD_LOGIC;
en:BUFFER std_logic_vector(2 downto 0)); ---使能输出 end;
architecture behave of record1 is begin
process(clr,RST) begin
if clr='0' then en<=\
elsif(RISING_edge(RST)) then
en<=en+1; end if; end process; end;
LIBRARY IEEE;
use ieee.std_logic_1164.all;
ENTITY DFF1 IS ------4位D触发器 PORT(
clr:in std_logic;
en:in std_logic_vector(2 downto 0);-----使能信号
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clk:in std_logic;
d1:in std_logic_vector(3 downto 0);------输入信号 q1:out std_logic_vector(3 downto 0)); END;
architecture behave of dff1 is
signal Q:std_logic_VECTOR(3 DOWNTO 0); BEGIN
PROCESS(CLR,CLK,EN) BEGIN
IF en=\ IF CLR='0' THEN Q<=\
ELSIF RISING_EDGE(CLK) THEN Q<=d1; END IF; END IF; END PROCESS; Q1<=Q; END;
LIBRARY IEEE;
use ieee.std_logic_1164.all;
ENTITY DFF2 IS ------4位D触发器 PORT(
clr:in std_logic;
en:in std_logic_vector(2 downto 0);-----使能信号 clk:in std_logic;
d2:in std_logic_vector(3 downto 0);------输入信号 q2:out std_logic_vector(3 downto 0));
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END;
architecture behave of dff2 is
signal Q:std_logic_VECTOR(3 DOWNTO 0); BEGIN
PROCESS(CLR,CLK,EN) BEGIN
IF en=\ IF CLR='0' THEN Q<=\
ELSIF RISING_EDGE(CLK) THEN Q<=d2; END IF; END IF; END PROCESS; Q2<=Q; END;
LIBRARY IEEE;
use ieee.std_logic_1164.all;
ENTITY DFF3 IS ------4位D触发器 PORT(
clr:in std_logic;
en:in std_logic_vector(2 downto 0);-----使能信号 clk:in std_logic;
d3:in std_logic_vector(3 downto 0);------输入信号 q3:out std_logic_vector(3 downto 0)); END;
architecture behave of dff3 is
signal Q:std_logic_VECTOR(3 DOWNTO 0);
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BEGIN
PROCESS(CLR,CLK,EN) BEGIN
IF en=\ IF CLR='0' THEN Q<=\
ELSIF RISING_EDGE(CLK) THEN Q<=d3; END IF; END IF; END PROCESS; Q3<=Q; END;
LIBRARY IEEE;
use ieee.std_logic_1164.all;
ENTITY DFF4 IS ------4位D触发器 PORT(
clr:in std_logic;
en:in std_logic_vector(2 downto 0);-----使能信号 clk:in std_logic;
d4:in std_logic_vector(3 downto 0);------输入信号 q4:out std_logic_vector(3 downto 0)); END;
architecture behave of dff4 is
signal Q:std_logic_VECTOR(3 DOWNTO 0); BEGIN
PROCESS(CLR,CLK,EN) BEGIN
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IF en=\ IF CLR='0' THEN Q<=\
ELSIF RISING_EDGE(CLK) THEN Q<=d4; END IF; END IF; END PROCESS; Q4<=Q; END;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity REPLAY is -----------回放模块 port(clr:in std_logic; rsh:in std_logic;
pn:buffer std_logic_vector(2 downto 0)); ---使能输出 end;
architecture behave of replay is begin process(clr,rsh) begin
if clr='0' then pn<=\
ELSif (RISLING_EDGE(RSH)) then pn<=pn+1; end if; end process; end;
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