基于VHDL的数字密码器的设计
【摘 要】 本论文介绍了一种利用 EDA技术 和VHDL 语言，通过自顶向下的设计方法对数字
密码器进行设计，并在FPGA芯片EPF10K10LC84-4上实现。用FPGA 器件构造系统, 所有算法完全由硬件电路来实现, 使得系统的工作可靠性大为提高。由于FPGA 具有ISP （在系统可编程）功能, 当设计需要更改时, 只需更改FPGA 中的控制和接口电路, 利用EDA 工具将更新后的设计下载到FPGA 中即可, 无需更改外部电路的设计, 大大提高了设计的效率。因此, 采用FPGA 开发的数字系统, 不仅具有很高的工作可靠性, 其升级与改进也极其方便。本文设计的密码器采用6位密码, 比一般的四位密码锁具有更高的安全可靠性, 应用前景十分良好。
摘要 ······················································································································································································1 1 EDA技术概述 ······························································································································································3
1.1 现代电子设计方法—EDA技术 ················································································································· 3
1.1.1 EDA技术的发展历程 ························································································································· 3 1.1.2 EDA技术的基本特征 ························································································································· 3 1.1.3 EDA技术的发展趋势 ····························································································································· 4 1.2 硬件描述语言（VHDL）简介 ························································································································· 5 1.2.1 VHDL的产生与发展 ································································································································ 5 1.2.2 VHDL的基本特征 ···································································································································· 5 1.2.3 VHDL的设计流程 ···································································································································· 6 1.3 可编程逻辑器件（PLD）简介······················································································································· 7 1.3.1 PLD的发展历程 ······································································································································ 7 1.3.2 FPGA/CPLD简介 ······································································································································ 8 1.3.3用FPGA/CPLD进行开发的优点 ············································································································· 8
2 数字密码器的VHDL设计 ·······································································································································8
2.1 数字密码器的总体方案设计 ························································································································· 8 2.1.1 数字密码器的功能描述 ························································································································ 8 2.1.2 数字密码器的内部结构及模块划分 ··································································································· 9 2.1.3 数字密码器的工作过程 ······················································································································ 10 2.2 数字密码器的顶层设计 ·························································································································· 11 2.2.1 顶层模块的输入输出 ·························································································································· 11 2.2.1模块描述 ················································································································································ 11 2.2.2 VHDL设计 ·············································································································································· 12 2.3 数字密码器的底层设计 ······························································································································· 12 2.3.1 分频模块 ··············································································································································· 12 2.3.2 消抖同步模块 ······································································································································· 13 2.3.3 使能电路模块 ······································································································································· 14 2.3.4 密码预置输出模块 ······························································································································· 14 2.3.5 编码模块 ··············································································································································· 15 2.3.6 比较模块 ··············································································································································· 16 2.3.7 计数器选择模块 ··································································································································· 16 2.3.8 数码管显示译码模块 ·························································································································· 17 2.3.9 数码管扫描模块 ··································································································································· 17 2.3.10 指示电路模块 ····································································································································· 18
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2.3.11 误码模块 ············································································································································· 19 2.3.12 控制器模块 ········································································································································· 19
3 数字密码器的VHDL程序的编译、综合、仿真、验证 ········································································ 22
3.1 编译、综合 ···················································································································································· 22 3.2 模块仿真 ························································································································································ 22 3.2.1 顶层模块仿真 ······································································································································· 22 3.2.2 编码模块仿真 ······································································································································· 23 3.3 FPGA验证 ······················································································································································· 24
4 结束语 ········································································································································································· 24 致谢辞 ············································································································································· 错误！未定义书签。 参考文献 ········································································································································ 错误！未定义书签。 附录 程序清单 ····························································································································································· 24
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1 EDA技术概述
电子技术的发展，特别是专用集成电路（ASIC）设计技术的日趋进步和完善，推动了数字系统的迅猛发展。传统的“固定功能集成块+连线”的设计方法已不能满足实际需求，根据系统功能要求利用现代电子设计方法—EDA技术，采用自上而下的设计方式，设计出速度快、体积小、重量轻、功耗低的集成电路已成为必然趋势。
1.1 现代电子设计方法—EDA技术
EDA(Electronic Design Automation)即电子设计自动化，它的定义是指利用计算机来完成电子系统的设计。EDA技术就是指以计算机为工作平台、以EDA软件工具为开发环境、以硬件描述语言为设计
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语言、以可编程逻辑器件为实验载体、以ASIC和SoC为设计目标、以电子系统设计为应用方向的电子产品自动化设计过程。在现代电子设计技术领域中，EDA技术已成为主要的设计手段。采用EDA技术可以缩短电系统设计的开发周期，极大地提高了工作效率。
1.1.1 EDA技术的发展历程
EDA 技术不是某一学科的分支，或某种新的技能技术，应该是一门综合性学科。它融合多学科于一体，打破了软件和硬件间的壁垒，使计算机的软件技术与硬件实现、设计效率和产品性能合二为一，它代表了电子设计技术和应用技术的发展方向。就过去近30年的电子技术的发展历程，可大致将EDA技术的发展分为三个阶段。
第一阶段 20世纪70年代，集成电路制作方面，MOS工艺已得到广泛的应用。 可编程逻辑技术及其器件已经问世，计算机作为一种运算工具已在科研领域得到广泛的应用。而在后期，CAD的概念已见雏形。这一阶段人们开始利用计算机取代手工劳动，辅助进行集成电路版图编辑、PCB布局布线等工作。
第二阶段 20世纪80年代，集成电路设计进入了CMOS(互补场效应管)时代。 复杂可编程逻辑器件已进入商业应用，相应的辅助设计软件也已投入使用，而在80年代末，出现了FPGA，CAE和CAD技术的应用更为广泛，它们在PCB设计方面的原理图输入、自动布局布线及PCB分析，以及逻辑设计、逻辑仿真、布尔方程综合和化简等方面担任了重要的角色，特别是各种硬件描述语言的出现、应用和标准化方面的重大进步，为电子设计自动化必须解决的电路建模、标准文档及仿真测试奠定了基础。
第三阶段 进入20世纪90年代，随着硬件描述语言的标准化得到进一步的确立，计算机辅助工程、辅助分析和辅助设计在电子技术领域获得更加广泛的应用，与此同时电子技术在通信、计算机及家电产品生产中的市场需求和技术需求，极大地推动了全新的电子设计自动化技术的应用和发展。特别是集成电路设计工艺步入了超深亚微米阶段，百万门以上的大规模ASIC设计技术的应用，促进了EDA技术的形成。更为重要的是各EDA公司致力于兼容各种硬件实现方案和支持标准硬件描述语言的EDA工具软件的研究,都有效地将EDA技术推向成熟。
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1.1.2 EDA技术的基本特征
EDA代表了当今电子设计技术的最新发展方向，它的基本特征是：设计人员按照“自顶向下”的设
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计方法，对整个系统进行方案设计和功能划分，系统的关键电路用一片或几片专用集成电路（ASIC）实现，然后采用硬件描述语言（HDL）完成系统行为级设计，最后通过综合器和适配器生成最终的目标器
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件，这样的设计方法被称为高层次的电子设计方法。下面介绍与EDA基本特征有关的几个概念。
1、 〝自顶向下〞的设计方法
“自顶向下”的设计方法首先从系统级设计入手，在顶层进行功能方框图的划分和结构设计；在方框图级进行仿真、纠错，并用硬件描述语言对高层次的系统行为进行描述；在功能级进行验证，然后用逻辑综合优化工具生成具体的门级逻辑电路的网表，其对应的物理实现级可以是印刷电路板或专用集成电路。“Top-down”设计方法有利于在早期发现结构设计中的错误，提高设计的一次成功率，因而在现代EDA系统中被广泛采用。
2、 硬件描述语言(HDL)
用硬件描述语言进行电路与系统的设计是当前EDA技术的一个重要特征。与传统的原理图输入设计方法相比较，硬件描述语言更适合于规模日益增大的电子系统，它还是进行逻辑综合优化的重要工具。硬件描述语言使得设计者在比较抽象的层次上描述设计的结构和内部特征。它的突出优点是：语言的公开可利用性；设计与工艺的无关性；宽范围的描述能力；便于组织大规模系统的设计；便于设计的复用和继承等。目前最常用的硬件描述语言有VHDL和Verilog-HDL，它们都已经成为IEEE标准。
3、 逻辑综合优化
逻辑综合功能将高层次的系统行为设计自动翻译成门级逻辑的电路描述，做到了设计与工艺的独立。优化则是对于上述综合生成的电路网表，根据布尔方程功能等效的原则，用更小更快的综合结果替代一些复杂的逻辑电路单元，根据指定的目标库映射成新的网表。
4、 开放性和标准化
框架是一种软件平台结构，它为EDA工具提供了操作环境。框架的关键在于提供与硬件平台无关的图形用户界面以及工具之间的通信、设计数据和设计流程的管理等，此外还应包括各种与数据库相关的服务项目。任何一个EDA系统只要建立了一个符合标准的开放式框架结构，就可以接纳其他厂商的EDA工具一起进行设计工作。这样，框架作为一套使用和配置EDA软件包的规范，就可以实现各种EDA工具间的优化组合，并集成在一个易于管理的统一的环境之下，实现资源共享。
5、ASIC设计
现代电子产品的复杂度日益提高，一个电子系统可能由数万个中小规模集成电路构成，这就带来了体积大、功耗大、可靠性差的问题。解决这一问题的有效方法就是采用ASIC芯片进行设计。ASIC按照设计方法的不同可分为全定制ASIC、半定制ASC和可编程ASIC（也称为可编程逻辑器件）。
设计全定制ASIC芯片时，设计师要定义芯片上所有晶体管的几何图形和工艺规则，最后将设计结果交由m厂家去进行格模制造，做出产品。这种设计方法的优点是芯片可以获得最优的性能，即面积利用率高、速度快、功耗低，而缺点是开发周期长，费用高，只适合大批量产品开发。
半定制ASIC芯片的版图设计方法分为门阵列设计法和标准单元设计法，这两种方法都是约束性的设计方法，其主要目的就是简化设计，以牺牲芯片性能为代价来缩短开发时间。
可编程逻辑芯片与上述掩模ASIC的不同之处在于：设计人员完成版图设计后，在实验室内就可以烧制出自己的芯片，无须IC厂家的参与，大大缩短了开发周期。
可编程逻辑器件自70年代以来，经历了PAL、GAL、CPLD、FPGA几个发展阶段，其中CPLD／FPGA高密度可编程逻辑器件，目前集成度已高达200万门／片，它将格模ASC集成度高的优点和可编程逻辑器件设计生产方便的特点结合在一起，特别适合于样品研制或小批量产品开发，使产品能以最快的速度上市，而当市场扩大时，它可以很容易地转由掩模ASIC实现，因此开发风险也大为降低。
上述ASIC芯片，尤其是CPLD／FPGA器件，已成为现代高层次电子设计方法的实现载体。
1.1.3 EDA技术的发展趋势
随着大规模集成电路技术和计算机技术的不断发展，在涉及工业自动化、计算机应用、仪器仪表等领域的电子系统设计工作中，EDA技术的含量正以惊人的速度上升，电子类的高新技术项目的开发也日
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益依赖于EDA技术的应用。即使是普通的电子产品的开发，EDA技术常常使一些原来的技术瓶颈得以
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轻松突破，从而使产品的开发周期大为缩短、性能价格比大幅度提高。所以EDA技术将成为电子设计领域中的极其重要的组成部分。电子设计专家认为，单片机时代己经结束，未来将是EDA的时代。随着微电子技术的飞速进步，电子学进入了一个崭新的时代。其特征是电子技术的应用以空前规模和速度渗透到各行各业。各行业对自己专用集成电路(ASIC)的设计要求日趋迫切，可编程器件的广泛应用，为各行业的电子系统设计工程师自行开发本行业专用的ASIC提供了技术和物质条件。与单片机系统开发相比，利用EDA技术对FPGA/CPLD的开发，通常是一种借助于软件的纯硬件开发，可以通过这种途径进行专用ASIC开发，而最终的ASIC芯片，可以是FPGA/CPLD，也可以是专制的门阵列掩模芯片，FPGA/CPLD起到了硬件仿真ASIC芯片的作用。
1.2 硬件描述语言（VHDL）简介
EDA技术的设计语言是硬件描述语言HDL，它采用软件编程的方式来描述电子系统的逻辑功能、电路结构和连接方式等。利用这种语言，数字电路系统的设计可以从上层到下层（从抽象到具体）逐层描述自己的设计思想，用一系列分层次的模块来表示极其复杂的数字系统。然后，利用电子设计自动化（EDA）工具，逐层进行仿真验证，再把其中需要变为实际电路的模块组合，经过自动综合工具转换到门级电路网表。接下去，再用专用集成电路ASIC或现场可编程门阵列FPGA自动布局布线工具，把网表转换为要实现的具体电路布线结构。
1.2.1 VHDL的产生与发展
美国于1981年提出了一种新的、标准化的HDL，称之为VHSIC（Very High Speed Integrated Circuit） Hardware Description Language，简称VHDL。这是一种用形式化方法来描述数字电路和设计数字逻辑系统的语言。设计者可以利用这种语言来描述自己的设计思想，然后利用电子设计自动化工具进行仿真，再自动综合到门级电路，最后用PLD实现其功能。1987年底，VHDL被IEEE和美国国防部确认为标准硬件描述语言 。自IEEE公布了VHDL的标准版本，IEEE-1076（简称87版)之后，各EDA公司相继推出了自己的VHDL设计环境，或宣布自己的设计工具可以和VHDL接口。此后VHDL在电子设计领域得到了广泛的接受，并逐步取代了原有的非标准的硬件描述语言。1993年，IEEE对VHDL进行了修订，从更高的抽象层次和系统描述能力上扩展VHDL的内容，公布了新版本的VHDL，即IEEE标准的1076-1993版本，（简称93版）。
现在，VHDL和Verilog作为IEEE的工业标准硬件描述语言，又得到众多EDA公司的支持，在电子工程领域，已成为事实上的通用硬件描述语言。有专家认为，在新的世纪中，VHDL和Verilog语言将承担起大部分的数字系统设计任务。
1.2.2 VHDL的基本特征
与其它的硬件描述语言相比，VHDL具有更强的行为描述能力，能够避开具体的器件结构，从行为功能上对数字电路系统设计进行描述。VHDL具有如下的基本特征：
1、设计功能强、方法灵活、支持广泛。VHDL语言可以支持自上而下的设计方法，它具有功能强大的语言结构，可用简洁明确的代码描述来进行复杂控制逻辑的设计，可硕士学位论文绪论以支持同步电路、异步电路、以及其他随机电路的设计。其范围之广是其他HDL语言所不能比拟的。此外，VHDL语言可以自定义数据类型，这也给编程人员带来了较大的自由和方便。
2、系统硬件描述能力强。VHDL语言具有多层次的设计描述功能，可以从系统的数字模型直到门级电路，支持设计库和可重复使用的元件生成，它支持阶层设计且提供模块设计的创建。VHDL语言能进行系统级的硬件描述是它的一个最突出的优点。
3、可以进行与工艺无关编程。VHDL语言设计系统硬件时，没有嵌入描述与工艺相关的信息，不会因为工艺变化而使描述过时。与工艺技术有关的参数可通过VHDL提高的类属加以描述，工艺改变时，只需修改相应程序中的类属参数即可。
4、VHDL语言标准、规范，易于共享和复用。VHDL既是IEEE承认的标准，故VHDL的描述可以被不同的EDA设计工具所支持。从一个仿真工具移植到另一个仿真工具，从一个综合工具移植到另一个综合
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