WHEN \ WHEN \ WHEN OTHERS => data <= \ END CASE; END PROCESS; sel <= count; END rtl;
8、 使能电路模块(enable_model.vhd ) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY enable_model IS
PORT(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9: IN std_logic; en: IN std_logic;
a00,a10,a20,a30,a40,a50,a60,a70,a80,a90: OUT std_logic); END enable_model;
ARCHITECTURE enable_model_arch OF enable_model IS BEGIN
PROCESS(en,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9) BEGIN
IF(en='1') THEN a00 <= a0; a10 <= a1; a20 <= a2; a30 <= a3; a40 <= a4; a50 <= a5; a60 <= a6; a70 <= a7; a80 <= a8; a90 <= a9; ELSE
a00 <= '1'; a10 <= '1'; a20 <= '1'; a30 <= '1'; a40 <= '1'; a50 <= '1'; a60 <= '1'; a70 <= '1'; a80 <= '1'; a90 <= '1'; END IF; END PROCESS; END enable_model_arch;
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9、 密码预置输出模块(mux4_model.vhd ) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY mux4_model IS
PORT(s0,s1,s2 : IN std_logic;
e1,e2,e3,e4 : OUT std_logic); END mux4_model;
ARCHITECTURE mux4_model_arch OF mux4_model IS SIGNAL comb : std_logic_vector(2 DOWNTO 0); BEGIN
comb <= s2&s1&s0; PROCESS(comb) BEGIN
IF(comb=\
e1 <= '0'; e2 <='1'; e3 <='1'; e4 <='0'; ELSIF(comb=\
e1 <= '1'; e2 <='0'; e3 <='1'; e4 <='0'; ELSIF(comb=\
e1 <= '0'; e2 <='0'; e3 <='1'; e4 <='0'; ELSIF(comb=\
e1 <= '1'; e2 <='1'; e3 <='0'; e4 <='0'; ELSIF(comb=\
e1 <= '0'; e2 <='1'; e3 <='0'; e4 <='0'; ELSIF(comb=\
e1 <= '1'; e2 <='0'; e3 <='0'; e4 <='0'; ELSE
e1 <= '1'; e2 <='1'; e3 <='1'; e4 <='1'; END IF; END PROCESS; END mux4_model_arch;
10、编码模块(encoder_model.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY encoder_model IS
PORT(a01,a11,a21,a31,a41,a51,a61,a71,a81,a91 : IN std_logic; reset,dus : IN std_logic; b1,b2,b3,b4 : OUT std_logic; data_in,di : OUT std_logic;
in1,in2,in3,in4,in5,in6 : OUT std_logic_vector(3 DOWNTO 0)); END encoder_model;
ARCHITECTURE encoder_model_arch OF encoder_model IS SIGNAL count : integer RANGE 0 TO 7; SIGNAL duw,d_in: std_logic;
SIGNAL data_tmp,io1,io2,io3,io4,io5,io6 : std_logic_vector(3 DOWNTO 0);
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BEGIN
PROCESS(a01,a11,a21,a31,a41,a51,a61,a71,a81,a91) BEGIN
IF(a01='1') THEN
data_tmp <= \
b1 <= '0'; b2 <='0'; b3 <='0'; b4 <='0'; d_in <='1';
ELSIF(a11='1') THEN data_tmp <= \
b1 <= '1'; b2 <='0'; b3 <='0'; b4 <='0'; d_in <='1';
ELSIF(a21='1') THEN data_tmp <= \
b1 <= '0'; b2 <='1'; b3 <='0'; b4 <='0'; d_in <='1';
ELSIF(a31='1') THEN data_tmp <= \
b1 <= '1'; b2 <='1'; b3 <='0'; b4 <='0'; d_in <='1';
ELSIF(a41='1') THEN data_tmp <= \
b1 <= '0'; b2 <='0'; b3 <='1'; b4 <='0'; d_in <='1';
ELSIF(a51='1') THEN data_tmp <= \
b1 <= '1'; b2 <='0'; b3 <='1'; b4 <='0'; d_in <='1';
ELSIF(a61='1') THEN data_tmp <= \
b1 <= '0'; b2 <='1'; b3 <='1'; b4 <='0'; d_in <='1';
ELSIF(a71='1') THEN data_tmp <= \
b1 <= '1'; b2 <='1'; b3 <='1'; b4 <='0'; d_in <='1';
ELSIF(a81='1') THEN data_tmp <= \
b1 <= '0'; b2 <='0'; b3 <='0'; b4 <='1'; d_in <='1';
ELSIF(a91='1') THEN data_tmp <= \
b1 <= '1'; b2 <='0'; b3 <='0'; b4 <='1'; d_in <='1'; ELSE
b1 <= '1'; b2 <='1'; b3 <='1'; b4 <='1'; d_in <='0';
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END IF;
END PROCESS;
PROCESS(d_in,reset) BEGIN
IF(reset='1') THEN di <= '0';
ELSIF(duw = '1') THEN di <= '0';
ELSIF(d_in='1') THEN di <= '1'; ELSE
di <= '0'; END IF;
END PROCESS;
PROCESS(dus,reset) BEGIN
IF(reset='1') THEN
count <= 0; duw <= '0';
ELSIF(dus'event AND dus='1') THEN IF(count>=5) THEN duw <= '1'; count <= 6; ELSE
count <= count+1; END IF; END IF;
END PROCESS;
PROCESS(count,dus) BEGIN
IF(count=0) THEN io1 <= \ io2 <= \ io3 <= \ io4 <= \ io5 <= \ io6 <= \
ELSIF(dus'event AND dus='0') THEN io6 <= data_tmp; io5 <= io6; io4 <= io5; io3 <= io4; io2 <= io3;
io1 <= io2; END IF;
END PROCESS; data_in <= d_in;
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in1 <= io1; in2 <= io2; in3 <= io3; in4 <= io4; in5 <= io5; in6 <= io6;
END encoder_model_arch;
11、比较模块(comparator_model.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY comparator_model IS
PORT(b1,b2,b3,b4: IN std_logic; e1,e2,e3,e4: IN std_logic; dep : OUT std_logic); END comparator_model;
ARCHITECTURE comparator_model_arch OF comparator_model IS BEGIN
PROCESS(b1,b2,b3,b4,e1,e2,e3,e4) BEGIN
IF(b1=e1 AND b2=e2 AND b3=e3 AND b4=e4) THEN dep <= '1'; ELSE
dep <= '0'; END IF; END PROCESS;
END comparator_model_arch;
12、计数器选择模块LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY counter_model IS
PORT(reset : IN std_logic; cnp : IN std_logic; s0,s1,s2 : OUT std_logic; full : OUT std_logic); END counter_model;
ARCHITECTURE counter_model_arch OF counter_model IS BEGIN
PROCESS(reset,cnp)
VARIABLE count: std_logic_vector(2 DOWNTO 0); BEGIN
IF (reset ='1') THEN count := \ full <= '0';
(counter_model.vhd) 35