cnp,reset : OUT std_logic; ds,ret : OUT std_logic;
s_lr,s_lg,wait_l: OUT std_logic); END COMPONENT;
COMPONENT clkdiv_model
PORT(clk : IN std_logic;
clk_div1 : OUT std_logic; clk_div2 : OUT std_logic); END COMPONENT;
COMPONENT keyscan_model
PORT(clkscan,reset : IN std_logic; in1,in2,in3,in4,
in5,in6,in7,in8 : IN std_logic_vector(3 DOWNTO 0); data : OUT std_logic_vector(3 DOWNTO 0); sel : OUT std_logic_vector(2 DOWNTO 0)); END COMPONENT;
COMPONENT wrong3_model
PORT(anc,ds : IN std_logic; clk,ret: IN std_logic;
in7,in8: OUT std_logic_vector(3 DOWNTO 0); notc,dsw : OUT std_logic; bjy : OUT std_logic); END COMPONENT;
SIGNAL e1,e2,e3,e4 : std_logic; SIGNAL b1,b2,b3,b4 : std_logic; SIGNAL dus,di,bjy : std_logic; SIGNAL anc,ds,ret : std_logic; SIGNAL notc,dsw : std_logic; SIGNAL c11,c22,c33,c44 : std_logic;
SIGNAL a00,a10,a20,a30,a40,a50,a60,a70,a80,a90 : std_logic; SIGNAL a01,a11,a21,a31,a41,a51,a61,a71,a81,a91 : std_logic; SIGNAL en,data_in : std_logic;
SIGNAL wait_l,s_lg,s_lr : std_logic; SIGNAL reset,cnp : std_logic; SIGNAL full,dep : std_logic; SIGNAL s0,s1,s2 : std_logic;
SIGNAL clk_div1,clk_div2 : std_logic;
SIGNAL data : std_logic_vector(3 DOWNTO 0);
SIGNAL in1,in2,in3,in4,in5,in6,in7,in8 : std_logic_vector(3 DOWNTO 0); BEGIN
U1: keysync_model
PORT MAP(wait_t,setup,ready,open_t,a00,a10,a20,a30,a40,a50,a60,a70,a80,a90, clk_div1,c11,c22,c33,c44,a01,a11,a21,a31,a41,a51,a61,a71, a81,a91); U2: enable_model
PORT MAP(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,en,a00,a10,
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a20,a30,a40,a50,a60,a70,a80,a90); U3: mux4_model
PORT MAP(s0,s1,s2,e1,e2,e3,e4); U4: encoder_model
PORT MAP(a01,a11,a21,a31,a41,a51,a61,a71,a81,a91,reset,dus,b1, b2,b3,b4,data_in,di,in1,in2,in3,in4,in5,in6); U5: comparator_model
PORT MAP(b1,b2,b3,b4,e1,e2,e3,e4,dep); U6: counter_model
PORT MAP(reset,cnp,s0,s1,s2,full); U7: decoder_model
PORT MAP(data,a,b,c,d,e,f,g); U8: indicator_model
PORT MAP(wait_l,s_lg,s_lr,di,bjy,clk,led_g,led_r,alert); U9:control_model
PORT MAP(c11,c22,c33,c44,data_in,dep,dsw,full,notc,clk_div1,en,dus,anc,cnp,reset, ds,ret,s_lr,s_lg,wait_l); U10:clkdiv_model
PORT MAP(clk,clk_div1,clk_div2); U11:keyscan_model
PORT MAP(clk,reset,in1,in2,in3,in4,in5,in6,in7,in8,data, sel);
U12:wrong3_model
PORT MAP(anc,ds,clk_div2,ret,in7,in8,notc,dsw,bjy); END cipher_top_arch;
2、 30分频单元电路(clk_div30.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY clk_div30 IS
PORT(clk : IN std_logic;
clk_div : OUT std_logic); END clk_div30;
ARCHITECTURE behave OF clk_div30 IS BEGIN
PROCESS(clk)
VARIABLE count:std_logic_vector(3 DOWNTO 0); VARIABLE clk_tmp: std_logic; BEGIN
IF(clk'event AND clk='1') THEN IF(count=\
count := (OTHERS => '0'); clk_tmp := NOT clk_tmp; ELSE
count := count+1;
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END IF; END IF;
clk_div <= clk_tmp; END PROCESS; END behave;
3、 10分频单元电路(clk_div10.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY clk_div10 IS
PORT(clk : IN std_logic;
clk_div : OUT std_logic); END clk_div10;
ARCHITECTURE behave OF clk_div10 IS BEGIN
PROCESS(clk)
VARIABLE count:std_logic_vector(2 DOWNTO 0); VARIABLE clk_tmp: std_logic; BEGIN
IF(clk'event AND clk='1') THEN IF(count=\
count := (OTHERS => '0'); clk_tmp := NOT clk_tmp; ELSE
count := count+1; END IF; END IF;
clk_div <= clk_tmp; END PROCESS; END behave;
4、 分频模块(clkdiv_model.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY clkdiv_model IS
PORT(clk : IN std_logic;
clk_div1 : OUT std_logic; clk_div2 : OUT std_logic); END clkdiv_model;
ARCHITECTURE clkdiv_model_arch OF clkdiv_model IS COMPONENT clk_div30
PORT(clk : IN std_logic; clk_div : OUT std_logic); END COMPONENT;
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COMPONENT clk_div10
PORT(clk : IN std_logic; clk_div : OUT std_logic); END COMPONENT;
SIGNAL tmp1 : std_logic; BEGIN
U1 : clk_div30
PORT MAP(clk,tmp1); U2 : clk_div10
PORT MAP(tmp1,clk_div2); clk_div1 <= tmp1; END clkdiv_model_arch;
5、 D触发器模块(dff_1.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY dff_1 IS
PORT(d,clk :IN std_logic; q,qb :OUT std_logic); END dff_1;
ARCHITECTURE rtl OF dff_1 IS BEGIN
PROCESS(clk) BEGIN
IF(clk'event AND clk='1') THEN q <=d;
qb<= NOT d; END IF; END PROCESS; END rtl;
6、 消抖同步电路(key_sync.vhd ) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY key_sync IS PORT(
key_in : IN STD_LOGIC; clk : IN STD_LOGIC; key_out : OUT STD_LOGIC); END key_sync;
ARCHITECTURE a OF key_sync IS COMPONENT dff_1 PORT(
d,clk :IN STD_LOGIC; q,qb :OUT STD_LOGIC); END COMPONENT;
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SIGNAL tmp1,tmp2,tmp3,tmp4,tmp5,tmp6 :std_logic; BEGIN
tmp2 <=key_in NAND tmp1; tmp1 <=tmp3 NAND tmp2; key_out <= tmp4 AND tmp5; U1:dff_1
PORT MAP(tmp2,clk,tmp4,tmp3); U2:dff_1
PORT MAP(tmp4,clk,tmp6,tmp5); END a;
7、 消抖同步模块LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY keyscan_model IS
PORT(clkscan,reset : IN std_logic; in1,in2,in3,in4,
in5,in6,in7,in8 : IN std_logic_vector(3 DOWNTO 0); data : OUT std_logic_vector(3 DOWNTO 0); sel : OUT std_logic_vector(2 DOWNTO 0)); END keyscan_model;
ARCHITECTURE rtl OF keyscan_model IS
SIGNAL count: std_logic_vector(2 DOWNTO 0); BEGIN
PROCESS(clkscan,reset) BEGIN
IF(reset='1') THEN count <= \
ELSIF(clkscan'event AND clkscan='1') THEN IF(count=\
count <=\ ELSE
count <= count+1; END IF; END IF;
END PROCESS; PROCESS(count) BEGIN
CASE count IS
WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \
(keysync_model.vhd ) 30