ELSIF(cnp'event AND cnp='1') THEN IF(count =\ count := count+1; full <= '1'; ELSE
count := count+1; END IF; END IF;
s0 <= count(0); s1 <= count(1); s2 <= count(2); END PROCESS; END counter_model_arch;
13、数码管显示译码模块LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY decoder_model IS
PORT(data: IN std_logic_vector(3 DOWNTO 0); a,b,c,d,e,f,g: OUT std_logic); END decoder_model;
ARCHITECTURE decoder_model_arch OF decoder_model IS SIGNAL data_tmp: std_logic_vector(6 DOWNTO 0); BEGIN
PROCESS(data) BEGIN
CASE data IS
WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS => data_tmp <=\ END CASE; END PROCESS; a<=data_tmp(0); b<=data_tmp(1); c<=data_tmp(2); d<=data_tmp(3); e<=data_tmp(4);
(decoder_model.vhd) 36
f<=data_tmp(5); g<=data_tmp(6); END decoder_model_arch;
14、数码管扫描模块(keyscan_model.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY keyscan_model IS
PORT(clkscan,reset : IN std_logic; in1,in2,in3,in4,
in5,in6,in7,in8 : IN std_logic_vector(3 DOWNTO 0); data : OUT std_logic_vector(3 DOWNTO 0); sel : OUT std_logic_vector(2 DOWNTO 0)); END keyscan_model;
ARCHITECTURE rtl OF keyscan_model IS
SIGNAL count: std_logic_vector(2 DOWNTO 0); BEGIN
PROCESS(clkscan,reset) BEGIN
IF(reset='1') THEN count <= \
ELSIF(clkscan'event AND clkscan='1') THEN IF(count=\
count <=\ ELSE
count <= count+1; END IF; END IF;
END PROCESS; PROCESS(count) BEGIN
CASE count IS
WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS => data <= \ END CASE; END PROCESS; sel <= count; END rtl;
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15、RS触发器单元电路(rs_dff.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY rs_dff IS
PORT(r,s : IN std_logic; q : OUT std_logic); END rs_dff;
ARCHITECTURE rtl OF rs_dff IS SIGNAL tmp1,tmp2 : std_logic; BEGIN
tmp2 <= r NAND tmp1; tmp1 <= tmp2 NAND s; q <= tmp1; END rtl;
16、指示电路模块(indicator_model.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY indicator_model IS
PORT(wait_l : IN std_logic; s_lg : IN std_logic; s_lr : IN std_logic; di,bjy : IN std_logic; clk_div1 : IN std_logic;
led_g,led_r,alert: OUT std_logic); END indicator_model;
ARCHITECTURE indicator_model_arch OF indicator_model IS COMPONENT rs_dff
PORT(r,s : IN std_logic; q : OUT std_logic); END COMPONENT;
SIGNAL tmp1 : std_logic; BEGIN
U1: rs_dff
PORT MAP(wait_l,s_lg,led_g); U2: rs_dff
PORT MAP(wait_l,s_lr,tmp1);
alert <= ((tmp1 AND clk_div1) OR di) OR bjy ; led_r <= tmp1 OR bjy; END indicator_model_arch;
17、误码模块(wrong3_model.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
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USE IEEE.std_logic_unsigned.ALL; ENTITY wrong3_model IS
PORT(anc,ds : IN std_logic; clk,ret: IN std_logic;
in7,in8 : OUT std_logic_vector(3 DOWNTO 0); notc,dsw : OUT std_logic; bjy : OUT std_logic); END wrong3_model;
ARCHITECTURE behave OF wrong3_model IS SIGNAL count : integer RANGE 0 TO 3; SIGNAL xs : std_logic; BEGIN
PROCESS(ret,anc) BEGIN
IF(ret='1') THEN
notc <= '0'; count <= 0;
ELSIF(anc'event AND anc='1') THEN IF(count=2) THEN
count <= 3; notc <= '1'; ELSE
count <= count+1; END IF; END IF;
END PROCESS;
PROCESS(count,xs) BEGIN
IF(count=1) THEN IF(xs = '1') THEN
in7 <= \ ELSE
in7 <= \ END IF;
ELSIF(count=2) THEN IF(xs = '1') THEN
in7 <= \ ELSE
in7 <= \ END IF; ELSE
in7 <= \ END IF;
END PROCESS; PROCESS(ds,clk)
VARIABLE cnt : integer RANGE 0 TO 5; BEGIN
IF(ds='0') THEN
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cnt := 0; xs <= '0'; dsw <= '0'; ELSIF(clk'event AND clk='1') THEN IF(cnt=4) THEN
dsw <= '1'; xs <= '0'; ELSE
cnt := cnt+1; xs <= '1'; END IF; END IF;
END PROCESS;
bjy <= clk AND xs; END behave;
18、控制器模块(control_model.vhd) LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY control_model IS
PORT(c11,c22,c33,c44 : IN std_logic; data_in : IN std_logic; dep,dsw : IN std_logic; full,notc : IN std_logic; clk : IN std_logic; en,dus,anc: OUT std_logic; cnp,reset : OUT std_logic; ds,ret : OUT std_logic;
s_lr,s_lg,wait_l: OUT std_logic); END control_model;
ARCHITECTURE control_model_arch OF control_model IS TYPE state IS (QA,QB,QC,QD,QE,QF,QG); SIGNAL current_state :state := QA; BEGIN
PROCESS BEGIN
WAIT UNTIL clk'event AND clk ='1'; CASE current_state IS WHEN QA => en<='0';
IF (c11='0') THEN
current_state <= QA; ELSE
current_state <= QB; wait_l <= '0'; s_lg <= '1'; s_lr <= '1'; ret <= '1'; END IF;
WHEN QB => wait_l <= '1'; en<= '0'; ret <= '0';
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