CY<='1';
ZI<='0';
ELSIF(A=B)THEN
Y<='0';
ZI<='1';
ELSE
CY<='0';
ZI<='0';
END IF;
ELSIF(S1='1' AND S0='1')THEN --乘法
AA<='0'&A; BB<='0'&B; TEMP<=AA*BB;
BCDOUT<=TEMP(7 DOWNTO 0); CY<=TEMP(8);
IF(TEMP=\
ZI<='1';
ELSE
ZI<='0';
END IF;
ELSIF(S1='1' AND S0='0')THEN --自减1
AA<='0'&A;
TEMP<=AA-1;
BCDOUT<=TEMP(7 DOWNTO 0); CY<=TEMP(8);
IF(TEMP=\
ZI<='1';
ELSE
ZI<='0';
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END IF;
ELSE
BCDOUT<=\CY<='0'; ZI<='0';
END IF;
END PROCESS;
END A;
13.2: 状态条件寄存器单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY LS74 IS PORT(
LDFR:IN STD_LOGIC; CY,ZI:IN STD_LOGIC; FC,FZ:OUT STD_LOGIC );
END LS74;--状态寄存器 ARCHITECTURE A OF LS74 IS BEGIN
PROCESS(LDFR)
BEGIN
IF(LDFR'EVENT AND LDFR='1')THEN
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FC<=CY;
FZ<=ZI;
END IF;
END PROCESS;
END A;
13.3: 暂存寄存器单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY LS273 IS PORT(
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK:IN STD_LOGIC;
O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END LS273;--通用寄存器 ARCHITECTURE A OF LS273 IS BEGIN
PROCESS(CLK) BEGIN
IF(CLK'EVENT AND CLK='1')THEN O<=D; END IF; END PROCESS; END A;
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13.4: 3选1数据选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX3 IS PORT(
ID:IN STD_LOGIC_VECTOR(7 DOWNTO 0); SW_B,CS:IN STD_LOGIC;
N1,N2:IN STD_LOGIC_VECTOR(7 DOWNTO 0); EW:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END MUX3;--3选1数据选择器单元 ARCHITECTURE A OF MUX3 IS BEGIN
PROCESS(SW_B,CS) BEGIN
IF(SW_B='0')THEN
EW<=ID;--从输入设备输入数据 ELSIF(CS='0')THEN
EW<=N2;--将ROM中读出的指令代码送入内部数据通路 ELSE
EW<=N1;--将5选1多路选择器的输出送入内部数据通路
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END IF; END PROCESS; END A;
13.5：5选1数据选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX5 IS PORT( );
END MUX5;--5选1数据选择器单元 ARCHITECTURE A OF MUX5 IS
SIGNAL SEL: STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN
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C,D,E,F,G: IN STD_LOGIC;
X1,X2,X3,X4,x5: IN STD_LOGIC_VECTOR(7 DOWNTO 0); W: out STD_LOGIC_VECTOR(7 DOWNTO 0)