IF(CLR='0')THEN UA<='0'; ELSIF(SE='0')THEN UA<='1';
ELSIF(T2'EVENT AND T2='1')THEN UA<=D; END IF; END PROCESS; END A;
13.11.3: 微地址转换器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY F1 IS PORT(
UA5,UA4,UA3,UA2,UA1,UA0:IN STD_LOGIC; D:OUT STD_LOGIC_VECTOR(5 DOWNTO 0) );
END F1;--微地址转换器 ARCHITECTURE A OF F1 IS
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BEGIN
D(5)<=UA5; D(4)<=UA4; D(3)<=UA3; D(2)<=UA2; D(1)<=UA1; D(0)<=UA0; END A;
13.11.4: 控制存储器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CONTROM IS
PORT(ADDR: IN STD_LOGIC_VECTOR(5 DOWNTO 0); UA:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); D:OUT STD_LOGIC_VECTOR(18 DOWNTO 0) );
END CONTROM;--操作控制器单元 ARCHITECTURE A OF CONTROM IS
SIGNAL DATAOUT: STD_LOGIC_VECTOR(24 DOWNTO 0); BEGIN
PROCESS(ADDR)
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BEGIN
CASE ADDR IS
WHEN \ WHEN \取指 WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \
WHEN \
WHEN \
WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS => DATAOUT<=\ END CASE;
UA(5 DOWNTO 0)<=DATAOUT(5 DOWNTO 0); D(18 DOWNTO 0)<=DATAOUT(24 DOWNTO 6); END PROCESS; END A;
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13.11.5: 微指令寄存器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MCOMMAND IS PORT(
T2,T3,T4,I3,I2,I1,I0:IN STD_LOGIC; O:IN STD_LOGIC_VECTOR(18 DOWNTO 0);
P1,P2,LOAD,LDPC,LDAR,LDIR,LDR0,LDR1,LDR2,LDR3,R0_B,R1_B,R2_B,R3_B,S1,S0,ALU_B,LDAC,LDDR,WR,CS,SW_B,LED_B,LDFR:OUT STD_LOGIC );
END MCOMMAND;--微地址寄存器 ARCHITECTURE A OF MCOMMAND IS
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SIGNAL DATAOUT:STD_LOGIC_VECTOR(18 DOWNTO 0); BEGIN
PROCESS(T2) BEGIN
IF(T2'EVENT AND T2='1')THEN
DATAOUT(18 DOWNTO 0)<=O(18 DOWNTO 0); END IF;
P2<=DATAOUT(0); P1<=DATAOUT(1);
LDFR<=DATAOUT(2) AND T4; LED_B<=DATAOUT(3); SW_B<=DATAOUT(4); CS<=DATAOUT(5);
WR<=DATAOUT(6)OR(NOT T3); LDDR<=DATAOUT(7) AND T4; LDAC<=DATAOUT(8) AND T4; ALU_B<=DATAOUT(9); S0<=DATAOUT(10); S1<=DATAOUT(11);
R3_B<=(DATAOUT(13)OR(NOT I1)OR (NOT I0))AND(DATAOUT(12)OR(NOT I3)OR (NOT I2));
R2_B<=(DATAOUT(13)OR(NOT I1)OR I0)AND(DATAOUT(12)OR(NOT I3)OR I2); R1_B<=(DATAOUT(13)OR(NOT I0)OR I1)AND(DATAOUT(12)OR(NOT I2)OR I3); R0_B<=(DATAOUT(13)OR I1 OR I0)AND(DATAOUT(12)OR I3 OR I2); LDR3<=T4 AND DATAOUT(14)AND I1 AND I0; LDR2<=T4 AND DATAOUT(14)AND I1 AND (NOT I0); LDR1<=T4 AND DATAOUT(14)AND (NOT I1) AND I0; LDR0<=T4 AND DATAOUT(14)AND (NOT I1) AND (NOT I0); LDIR<=DATAOUT(15)AND T3; LDAR<=DATAOUT(16)AND T3;
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