SEL<=G&F&E&D&C; PROCESS(SEL) BEGIN
IF(SEL=\ --输出R0的内容 W<=X1;
ELSIF(SEL=\ --输出R1的内容 W<=X2;
ELSIF(SEL=\ --输出R2的内容 W<=X3;
ELSIF(SEL=\ --输出R3的内容 W<=X4;
ELSIF(SEL=\ --输出ALU的内容 W<=X5; ELSE null; END IF; END PROCESS; END A;
13.6: 程序计数器单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
15
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PC IS PORT(
LOAD,LDPC,CLR:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END PC;--程序计数器 ARCHITECTURE A OF PC IS
SIGNAL QOUT:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
PROCESS(LDPC,CLR,LOAD) BEGIN
IF(CLR='0')THEN
QOUT<=\将pc清0 ELSIF(LDPC'EVENT AND LDPC='1')THEN IF(LOAD='0')THEN
QOUT<=D; --将数据总线的内容送入pc ELSE
QOUT<=QOUT+1; --PC+1 END IF; END IF; END PROCESS; O<=QOUT; END A;
16
13.7: 地址寄存器单元
13.8: 主存储器单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ROM16 IS PORT( );
END ROM16;--主存储器单元ROM16 ARCHITECTURE A OF ROM16 IS BEGIN
DOUT<=\ -- MOV R1,00
\
\ --MOV R2,00
17
DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); ADDR:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CS:IN STD_LOGIC
\
\ --MOV R3,05 \
\ -- L1: IN R0 \ -- DEC R3
\ -- CMP R2,R0 \ --JB L2
\
\ -- CMP R2,R3 \ -- JB: L1 \
\ -- JMP L3 \ --
\ --L2:MUL R0,R0
\ --ADD R0,R1 \ --CMP R2,R3 \ --JB L1 \ --
\ --L3:OUT1 R1 \END A;
13.9: 指令寄存器单元
18
13.10: 时序产生器单元
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER IS PORT(
Q,CLR:IN STD_LOGIC; T2,T3,T4:OUT STD_LOGIC );
END COUNTER;--时序产生器单元 ARCHITECTURE A OF COUNTER IS
SIGNAL X:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
PROCESS(Q,CLR) BEGIN
IF(CLR='0')THEN T2<='0'; T3<='0'; T4<='0'; X<=\
ELSIF(Q'EVENT AND Q='1')THEN--当出现时钟Q上边沿时，计数器的值X+1 X<=X+1;--由当前值X译码后产生节拍脉冲信号T2，T3，T4.
19