电子科技大学 硕士学位论文 基于FPGA的高速IIR数字滤波器设计与实现 姓名：罗海 申请学位级别：硕士 专业：通信与信息系统 指导教师：何旭 20070601
摘要
摘要
数字滤波器是现代数字信号处理系统的重要组成部分之一。IIR数字滤波器 又是其中非常重要的一类虑波器，因其可以较低的阶次获得较高的频率选择特性 而得到广泛应用。木文研究了IIR数字滤波器的常用设计方法，在分析各种IIR 实现结构的基础上，利用MATLAB针对并联型结构的IIR数字滤波器做了多方面 的仿真，从理论分析和仿真情况确定了所要设计的IIR数字滤波器的实现结构以 及中间数据精度。然后基于FPGA的结构特点，研究了IIR数字滤波器的FPGA 设计与实现，提出应用流水线技术和并行处理技术相结合的方式来提高IIR数字 滤波器处理速度的方法，同时又从IIR数字滤波器的结构特性出发，提出利用IIR 数字滤波器的分解技术来改善IIR滤波器的设计。在IIR实现方面，本文采用 Verilog HDL语言编写了相应的硬件实现程序，将内置SignalTap 11逻辑分析器的
IIR设计下载到FPGA芯片，并利用Altera公司的SignalTap II逻辑分析仪进行了 定性测试，同时利用HP频谱仪进行定性与定量的观测，仿真与实验测试结果表 明设计方法J下确有效。
关键词：数字滤波器，无限长单位冲激响应，现场可编程门阵列，MATLAB，Verilog 硬件描述语言
Abstract
Digital filter iS one of the important contents of digital signal process．With its good characteristic of frequency selection in lower order in comparison谢tll FIR．IIR digital filter is widely applied in modem signal processing systems．This paper has tO design stable IIR studied several common methods digital filter．Firstly,based on tlle
analysis of IIR basic realization architeetures．the arithmetic simulation using M
√^TLAB has been studied according to paralell realization architecture of IIR digital theoretic analysis，the final architecture and filter,and with the simulation results and data resolution of IIR filter has been decided．Secondly,the FPGA design and realization of IIR digital filter has been researched．In order to improve the speed and performance of IIR digital filter,on the one hand。from the structure of the FPGA。the pilelining technology and the parallel—process technology have been studied．On the the IIR digital filter,made 111Se：of the decomposing othel\，from the structure of to improve the design．TheSC have been validated simulation by technology and Verilog HDL program．At last，the 14”IIR di西tal filter has been designed and M棚，AB
downloaded into Stratix FPGA device．Compared the simulation resul招with the test results using Altera’S SignalTap II analyzer and HP’S frequency spectrum analyzer,the meet the request． design is Correct，and can
HDL Key Words：Digital Filter,IIR FPGA，MATLAB，Verilog
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