序列信号发生器的设计与实现
tmp<=tmp+1;
end if;
end if;
end process p1;
p2: process(clear,tmp)—第二个进程描述输出逻辑
begin
if clear='0' then
q_out<='0';
else
case tmp is
when 0|3|4 =>q_out<='0';
when others =>q_out<='1';
end case;
end if;
end process p2;
clk_outt<=clk;
end a;
2、M序列信号发生器
library IEEE;
USE IEEE. std_logic_1164.all;
entity m_xulie is
port (
clk:in std_logic;
q_out:out std_logic;
clk_outt:out std_logic);--用户定义的输出输入及类型
end m_xulie;
architecture a of m_xulie is
component div50m
port
(
clk_in:in std_logic;
clk_out:out std_logic
);--用户定义分频器的输入的输出及类型
end component;
signal tmp:std_logic_vector (2 downto 0);
signal clock: std_logic;
begin
u1: div50m port map(clk_in=>clk,clk_out=>clock);--分频器的引入 p1:process(clk)—第一个进程P1描述状态逻辑