Memory Hierarchy Overview
Table 1.TMS320C621x/C671x/C64x Internal Memory Comparison (Continued)
TMS320C621x/C671x DSPTMS320C64x DSP6 cycles/L2 SRAM hit8 cycles/L2 cache hit4 cycles for L2 hitL1D → L2 single request stall
L1D → L2 minimum cycles between
pipelined misses
L2 total size
L2 SRAM size
L2 cache size
L2 organization
L2 line size
L2 replacement strategy
L2 banking
L2-L1P protocol
L2-L1D protocol
L2 protocol
L2 read miss action
L2 read hit action
L2 write miss action
L2 write hit action
L2 → L1P read path width
L2 → L1D read path width
L1D → L2 write path width
L1D → L2 victim path width
L2 → EDMA read path width
L2 → EDMA write path width Pipelined misses not supported2 cyclesVaries by part number. Refer to the datasheet for the specific device.Varies by part number. Refer to the datasheet for the specific device.0/16/32/48/64 Kbytes1/2/3/4-way set associative0/32/64/128/256 Kbytes4-way set associative cache128 bytes1/2/3/4-way Least Recently Used4 × 64 bit banks4-way Least Recently Used8 × 64 bit banksCoherency invalidatesCoherency snoop-invalidatesCoherency snoops andsnoop-invalidatesRead and Write AllocateData is read via EDMA into newly allocated line in L2; requesteddata is passed to the requesting L1Data read from L2Data is read via EDMA into newly allocated line in L2; write data isthen written to the newly allocated line.Data is written into hit L2 location256 bit128 bit32 bit128 bit64 bit64 bit256 bit64 bit256 bitSome C64x devices may not support the 256K cache mode. Refer to the device-specific datasheet.
SPRU610BTMS320C64x Two-Level Internal Memory11