TMS320C64x Two-Level Internal Memory
The TMS320C621x, TMS320C671x, and TMS320C64x digital signal
processors (DSPs) of the TMS320C6000 DSP family have a two-level
memory architecture for program and data. The first-level program cache is
designated L1P, and the first-level data cache is designated L1D. Both the
program and data memory share the second-level memory, designated L2. L2
is configurable, allowing for various amounts of cache and SRAM. This
document discusses the C64x two-level internal memory. For a discussion
of the C621x/C671x two-level internal memory, see TMS320C621x/C671x DSP
Two-Level Internal Memory Reference Guide (SPRU609).
1Memory Hierarchy Overview
Figure 1 shows the block diagram of the C64x DSP. Table 1 summarizes the
differences between the C621x/C671x and C64x internal memory. Figure 2
illustrates the bus connections between the CPU, internal memories, and the
enhanced DMA (EDMA) of the C6000 DSP.
Figure 1.
TMS320C64x DSP Block Diagram
Note:EMIFB is available only on certain C64x devices. Refer to the device-specific data sheet for the available peripheral set.SPRU610BTMS320C64x Two-Level Internal Memory9