PrefaceRead This First
About This Manual
The TMS320C64x digital signal processors (DSPs) of the
TMS320C6000 DSP family have a two-level memory architecture for
program and data. The first-level program cache is designated L1P, and the
first-level data cache is designated L1D. Both the program and data memory
share the second-level memory, designated L2. L2 is configurable, allowing
for various amounts of cache and SRAM. This document discusses the C64x
two-level internal memory.
Notational Conventions
This document uses the following conventions.
-Hexadecimal numbers are shown with the suffix h. For example, thefollowing number is 40 hexadecimal (decimal 64): 40h.
-Registers in this document are shown in figures and described in tables.
JEach register figure shows a rectangle divided into fields that representthe fields of the register. Each field is labeled with its bit name, its
beginning and ending bit numbers above, and its read/write properties
below. A legend explains the notation used for the properties.
Reserved bits in a register figure designate a bit that is used for futuredevice expansion.J
Related Documentation From Texas Instruments
The following documents describe the C6000 devices and related support
tools. Copies of these documents are available on the Internet at http://www.77cn.com.cn.
Tip: Enter the literature number in the search box provided at http://www.77cn.com.cn.
TMS320C6000 CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the TMS320C6000 CPU architecture,
instruction set, pipeline, and interrupts for these digital signal processors.
TMS320C6000 DSP Peripherals Overview Reference Guide (literature
number SPRU190) describes the peripherals available on the
TMS320C6000 DSPs.
SPRU610BTMS320C64x Two-Level Internal Memory3