Tables
Tables
1TMS320C621x/C671x/C64x Internal Memory Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . 102Terms and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Cycles Per Miss for Different Numbers of L1D Misses That Hit L2 Cache. . . . . . . . . . . . . . 264Cycles Per Miss for Different Numbers of L1D Misses that Hit L2 SRAM. . . . . . . . . . . . . . . 265Average Miss Penalties for Large Numbers of Sequential Execute Packets. . . . . . . . . . . . 296Internal Memory Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387Cache Configuration Register (CCFG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 398L2 EDMA Access Control Register (EDMAWEIGHT) Field Descriptions. . . . . . . . . . . . . . . 419L2 Allocation Registers (L2ALLOC0 L2ALLOC3) Field Descriptions. . . . . . . . . . . . . . . . . . 4210L2 Writeback Base Address Register (L2WBAR) Field Descriptions. . . . . . . . . . . . . . . . . . . 4311L2 Writeback Word Count Register (L2WWC) Field Descriptions. . . . . . . . . . . . . . . . . . . . . 4312L2 Writeback Invalidate Base Address Register (L2WIBAR) Field Descriptions. . . . . . . . 4413L2 Writeback Invalidate Word Count Register (L2WIWC) Field Descriptions. . . . . . . . . . . 4414L2 Invalidate Base Address Register (L2IBAR) Field Descriptions. . . . . . . . . . . . . . . . . . . . 4515L2 Invalidate Word Count Register (L2IWC) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . 4516L1P Invalidate Base Address Register (L1PIBAR) Field Descriptions. . . . . . . . . . . . . . . . . 4617L1P Invalidate Word Count Register (L1PIWC) Field Descriptions. . . . . . . . . . . . . . . . . . . . 4618L1D Writeback Invalidate Base Address Register (L1DWIBAR) Field Descriptions. . . . . 4719L1D Writeback Invalidate Word Count Register (L1DWIWC) Field Descriptions. . . . . . . . 4720L1D Invalidate Base Address Register (L1DIBAR) Field Descriptions. . . . . . . . . . . . . . . . . 4821L1D Invalidate Word Count Register (L1DIWC) Field Descriptions. . . . . . . . . . . . . . . . . . . . 4822L2 Writeback All Register (L2WB) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4923L2 Writeback Invalidate All Register (L2WBINV) Field Descriptions. . . . . . . . . . . . . . . . . . . 5024Memory Attribute Register (MAR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5125L1D Mode Setting Using DCC Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5226L1P Mode Setting Using PCC Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5327L2 Mode Switch Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5528Memory Attribute Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5729Summary of Program-Initiated Cache Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6030L2ALLOC Default Queue Allocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6831Coherence Assurances in the Two-Level Memory System. . . . . . . . . . . . . . . . . . . . . . . . . . . 7032Program Order for Memory Operations Issued From a Single Execute Packet. . . . . . . . . 7633Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818T MS320C64x Two-Level Internal MemorySPRU610B