else if ( si_reg[ 7:0 ] == WRDI ) begin
//$display( $stime, \ write_disable;
//$display( $stime, \ state <= `STANDBY_STATE; end
else if ( si_reg[ 7:0 ] == RDID ) begin
//$display( $stime, \ read_id;
//$display( $stime, \
state <= `STANDBY_STATE; end
else if ( si_reg[ 7:0 ] == RDSR ) begin
//$display( $stime, \ read_status ( status_reg );
//$display( $stime, \
state <= `STANDBY_STATE; end
else if ( si_reg[ 7:0 ] == WRSR ) begin
//$display( $stime, \ write_status;
//$display( $stime, \
state <= `STANDBY_STATE; end
else if ( si_reg[ 7:0 ] == READ ) begin
$display( $stime, \ dummy_cycle( 24 ); // to get 24 bits address read_data;
//$display( $stime, \
state <= `STANDBY_STATE; end
else if ( si_reg[ 7:0 ] == FASTREAD ) begin
//$display( $stime, \ dummy_cycle( 24 ); // to get 24 bits address fast_read_data;
//$display( $stime, \ state <= `STANDBY_STATE; end
//else if ( si_reg[ 7:0 ] == PARALLELMODE ) begin
// //$display( $stime, \ // parallel_mode;
// //$display( $stime, \ // state <= `STANDBY_STATE; //end
else if ( si_reg[ 7:0 ] == SE ) begin
//$display( $stime, \ dummy_cycle( 24 ); // to get 24 bits address sector_erase;
//$display( $stime, \
state <= `STANDBY_STATE; end
else if ( si_reg[ 7:0 ] == BE ) begin
//$display( $stime, \ dummy_cycle( 24 ); // to get 24 bits address block_erase;
//$display( $stime, \
state <= `STANDBY_STATE; end
else if ( si_reg[ 7:0 ] == CE1 || si_reg[ 7:0 ] == CE2 ) begin //$display( $stime, \ chip_erase;
//$display( $stime, \ state <= `STANDBY_STATE; end
else if ( si_reg[ 7:0 ] == PP ) begin
//$display( $stime, \ dummy_cycle( 24 ); // to get 24 bits address setup_addr( si_reg, segment_addr, offset_addr ); page_program( segment_addr, offset_addr ); update_array( segment_addr, offset_addr );
//$display( $stime, \ state <= `STANDBY_STATE; end
else if ( si_reg[ 7:0 ] == DP ) begin
//$display( $stime, \ deep_power_down;
//$display( $stime, \ state <= `STANDBY_STATE; end
//else if ( si_reg[ 7:0 ] == EN4K ) begin
// //$display( $stime, \ // enter_4kb_sector;
// //$display( $stime, \ // state <= `STANDBY_STATE;
Function ...\
Function ...\
Function ...\
Function ...\
//end //else if ( si_reg[ 7:0 ] == EX4K ) begin
// //$display( $stime, \ // exit_4kb_sector;
// //$display( $stime, \ // state <= `STANDBY_STATE; //end else if ( si_reg[ 7:0 ] == RDP || si_reg[ 7:0 ] == RES ) begin
//$display( $stime, \Enter Release from Deep Power Dwon release_from_deep_power_dwon;
//$display( $stime, \Leave Release from Deep Power Dwon state <= `STANDBY_STATE; end else if ( si_reg[ 7:0 ] == REMS ) begin
//$display( $stime, \Enter Read Electronic Manufacturer & ID dummy_cycle ( 16 ); // 2 dummy cycle dummy_cycle ( 8 ); // 1 AD
read_electronic_manufacturer_device_id;
//$display( $stime, \Leave Read Electronic Manufacturer & ID state <= `STANDBY_STATE; end
else begin
state <= #1 `BAD_CMD_STATE; end end `BAD_CMD_STATE: begin
//SO <= #tSHQZ 1'bz; SO_reg <= #tSHQZ 1'bz;
state <= #(tC-1) `BAD_CMD_STATE; end
default: begin
SO_reg <= #tAA 1'bx;
state <= #(tC-1) `STANDBY_STATE; end endcase
end // else begin
end // always @( posedge SCLK or posedge CS ) begin
////////////////////////////////////////////////////////////////////// // Module Task Declaration
//////////////////////////////////////////////////////////////////////
/*---------------------------------------------------------------*/
/* Description: define a wait dummy cycle task /* INPUT /* cnum: cycle number /*---------------------------------------------------------------*/ task dummy_cycle; input [31:0] cnum;
begin
repeat( cnum ) begin
@( posedge SCLK ); end end endtask
/*---------------------------------------------------------------*/
/* Description: setup segment address and offset address from /* 4-byte serial input. /* INPUT /* si: 4-byte serial input /* OUTPUT /* segment: segment address /* offset : offset address /*---------------------------------------------------------------*/ task setup_addr;
input [23:0] si;
output [13:0] segment; output [7:0] offset;
*/
*/ */ */
*/
*/ */
*/ */ */
begin #1;
{ offset[ 7:0 ] } = { si_reg[ 7:0 ] }; { segment[ 13:0 ] } = { si_reg[ 23:8 ] }; end endtask
/*---------------------------------------------------------------*/
/* Description: setup sector address */
/* INPUT */ /* si: 2-byte serial input */
/* OUTPUT */ /* sector: sector address */ /*---------------------------------------------------------------*/ task setup_sector; input [23:0] si;
output [`SECTOR_ADDR -1:0] sector; // A[`SECTOR_ADDR -1:16] defines a sector
begin #1;
{ sector[`SECTOR_ADDR -1:0 ] } = { si_reg[ 11:4 ] }; end endtask
/*---------------------------------------------------------------*/
/* Description: define a write enable task */ /*---------------------------------------------------------------*/ task write_enable; begin
//$display( $stime, \ forever begin
@( posedge SCLK or posedge CS ); if ( CS == 1'b1 ) begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode status_reg[1] = 1'b1;
//$display( $stime, \ if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
end else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
end