end
disable write_enable; //disable描述，退出forever end
else begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} {1'b1,1'b0,1'b0,1'b0};
end else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} {1'b0,1'b1,1'b0,1'b0};
end end end end end endtask
/*---------------------------------------------------------------*/
/* Description: define a write disable task (WRDI) */ /*---------------------------------------------------------------*/ task write_disable; begin
//$display( $stime, \
if ( dpmode == 1'b0) begin //do work on non deep power down mode if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0}; end else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0}; end end forever begin
@( posedge SCLK or posedge CS ); if ( CS == 1'b1 ) begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} {1'b1,1'b0,1'b0,1'b0};
end else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} {1'b0,1'b1,1'b0,1'b0};
=
=
=
=
end
status_reg[1] = 1'b0;
//$display( $stime, \ end
disable write_disable; end
else begin end end end endtask
/*---------------------------------------------------------------*/
/* Description: define a read id task (WRID) */ /*---------------------------------------------------------------*/ task read_id;
reg [ 23:0 ] dummy_ID; integer dummy_count; begin
dummy_ID = {ID_MXIC,8'h20,ID_Device}; dummy_count = 0; if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0}; end else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0}; end
forever begin
@( negedge SCLK or posedge CS ); if ( CS == 1'b1 ) begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} {1'b1,1'b0,1'b0,1'b0};
end else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} {1'b0,1'b1,1'b0,1'b0};
end
SO_reg <= #tCLQV 1'bz; //SO = #tCLQV 1'bz; end
disable read_id; end
= = else begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode if ( pmode == 1'b0) begin // check parallel mode (2)
{ SO_reg, dummy_ID } <= #tCLQV { dummy_ID, dummy_ID[ 23 ] };
end
else begin
if ( dummy_count == 0 ) begin
SO_reg <= #tCLQV ID_MXIC; dummy_count = 1; end
else if ( dummy_count == 1 ) begin SO_reg <= #tCLQV 8'h00; dummy_count = 2; end
else if ( dummy_count == 2 ) begin SO_reg <= #tCLQV ID_Device; dummy_count = 0; end end end end
end // end forever end endtask
/*---------------------------------------------------------------*/
/* Description: define a read status task (WRSR) */ /*---------------------------------------------------------------*/ task read_status;
input [ 7:0 ] s_reg;
reg [ 7:0 ] dummy_reg; integer dummy_count; begin
dummy_reg = s_reg; dummy_count = 8;
if ( dpmode == 1'b0) begin //do work on non deep power down mode if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0}; end else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0}; end end
forever begin
@( negedge SCLK or posedge CS ); if ( CS == 1'b1 ) begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};
end else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0};
end
SO_reg <= #tCLQV 1'bz; //SO = #tCLQV 1'bz; end
disable read_status; end
else begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode if ( pmode == 1'b0 ) begin if (dummy_count) begin
{ SO_reg, dummy_reg } <= #tCLQV { dummy_reg, dummy_reg[ 7 ] };
dummy_count = dummy_count - 1; end
else begin
dummy_reg = s_reg;
{ SO_reg, dummy_reg } <= #tCLQV { dummy_reg, dummy_reg[ 7 ] };
dummy_count = 7; end end
else begin
SO_reg <= #tCLQV s_reg; end end end
end // end forever end endtask
/*---------------------------------------------------------------*/
/* Description: define a write status task */ /*---------------------------------------------------------------*/
task write_status;
integer dummy_count; begin
dummy_count=0;
//$display( $stime, \
if ( dpmode == 1'b0) begin //do work on non deep power down mode if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0}; end else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0}; end end forever begin
@( posedge SCLK or posedge CS ); if ( CS == 1'b1 ) begin
if ( dpmode == 1'b0) begin //do work on non deep power down mode if (pmode == 0) begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0}; end else begin
{ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b0,1'b1,1'b0,1'b0}; end
if ( !(wp_reg ==1'b0 && status_reg[7]==1'b1) ) begin // do work on not PM (2)
if ( status_reg[1] == 1'b1 ) begin //WEL:Write Enable Latch (3) if ( dummy_count == 8 ) begin
if( (status_reg[7] == si_reg[7] ) && (status_reg[5:2] == si_reg[5:2] )) begin
//WIP:Write Enable Latch status_reg[0] <= 1'b1;
status_reg[0] <= #tW_WEL 1'b0; //WEL:Write Enable Latch
status_reg[1] <= #tW_WEL 1'b0; end else begin
//SRWD:Status Register Write Protect status_reg[7] <= #tW_BP si_reg[7]; status_reg[5:2] <= #tW_BP si_reg[5:2]; //WIP:Write Enable Latch status_reg[0] <= 1'b1;
status_reg[0] <= #tW_BP 1'b0; //WEL:Write Enable Latch
status_reg[1] <= #tW_BP 1'b0;