tCH = 7, // Clock High Time (min) [ns] tCL = 7, // Clock Low Time (min) [ns]
tSLCH = 5, // CS Lead Clock Time (min) [ns] tCHSL = 5, // CS Lag Clock Time (min) [ns] tSHSL = 100, // CS High Time (min) [ns] tDVCH = 2, // SI Setup Time (min) [ns] tCHDX = 5; // SI Hold Time (min) [ns]
//====================================================== // Timing Check
//====================================================== $period( posedge SCLK , tCYC ); // SCLK _/~ -> _/~ $period( negedge SCLK , tCYC ); // SCLK ~\\_ -> ~\\_ $width ( posedge SCLK , tCH ); // SCLK _/~~\\_ $width ( negedge SCLK , tCL ); // SCLK ~\\__/~ $width ( posedge CS , tSHSL ); // CS _/~\\_
$setuphold( posedge SCLK &&& ~CS, SI, tDVCH, tCHDX ); $setup ( CS, posedge SCLK &&& ~CS, tSLCH ); $hold ( negedge SCLK &&& ~CS, CS, tCHSL );
endspecify endmodule