dummy_ID = {ID_MXIC,ID_Device+1}; end
else begin
dummy_ID = {ID_Device,ID_MXIC}; end
dummy_count = 0; forever begin
@( negedge SCLK or posedge CS ); if ( CS == 1'b1 ) begin
if ( dpmode == 1'b0 ) begin // do work on non deep power down mode SO_reg <= #tCLQV 1'bz; end
disable read_electronic_manufacturer_device_id; end
else begin
if ( dpmode == 1'b0 ) begin // do work on non deep power down mode if ( pmode == 1'b0) begin // check parallel mode (2)
{ SO_reg, dummy_ID } <= #tCLQV { dummy_ID, dummy_ID[ 15 ] };
end else begin
if ( dummy_count == 0 ) begin
SO_reg = #tCLQV dummy_ID[15:8]; dummy_count = 1; end
else begin
SO_reg = #tCLQV dummy_ID[7:0]; dummy_count = 0; end end end end
end // end forever end endtask
/*---------------------------------------------------------------*/
/* Description: define a program chip task */
/* INPUT */ /* segment: segment address */ /* offset : offset address */ /*---------------------------------------------------------------*/ task update_array;
input [12:0] segment; input [7:0] offset;
reg [`FLASH_ADDR - 1:0] rom_addr; // rom_addr = {segment, offset} integer dummy_count, tmp_int;
reg [`SECTOR_ADDR - 1:0] sector; begin
dummy_count = 256;
/*------------------------------------------------*/
/* Store 256 bytes back to ROM Page */ /*------------------------------------------------*/
if ( dpmode == 1'b0 ) begin // do work on non deep power down mode (1) if (status_reg[0] == 1'b0) begin // WIP (2)
sector[`SECTOR_ADDR - 1:0] = rom_addr[`FLASH_ADDR - 1:12]; if ( wp_reg !=1'b0 || status_reg[7]!=1'b1 ) begin // protected mode (3) if ( status_reg[1] == 1'b1 ) begin // WEL:Write Enable Latch (4) if ( protected_area(sector[`SECTOR_ADDR - 1:0]) == 1'b0 ) begin // check protected area (5)
// initial start rom addrress offset = 8'h00;
rom_addr[`FLASH_ADDR - 1:0] = { segment[12:0], offset[7:0] };
// in write operation status_reg[0]<= 1'b1;
// not in write operation after PROG_TIME status_reg[0]<= #`PROG_TIME 1'b0; // WEL : write enable latch
status_reg[1]<= #`PROG_TIME 1'b0; while ( dummy_count ) begin
rom_addr[`FLASH_ADDR - 1:0] = { segment[12:0], offset[7:0] };
dummy_count = dummy_count - 1;
tmp_int = dummy_count << 3; /* byte to bit */ ROM_ARRAY[ rom_addr ] <= #`PROG_TIME { dummy_A[ tmp_int+7 ], dummy_A[ tmp_int+6 ],
dummy_A[ tmp_int+5 ], dummy_A[ tmp_int+4 ],
dummy_A[ tmp_int+3 ], dummy_A[ tmp_int+2 ],
dummy_A[ tmp_int+1 ], dummy_A[ tmp_int ] };
offset = offset + 1;
end
end // end protected area
end // end WEL:Write Enable Latch end end end end endtask
/*---------------------------------------------------------------*/
/* Description: define a protected_area area function */
/* INPUT */ /* sector : sector address */ /*---------------------------------------------------------------*/ function protected_area; input [7:0] sector; begin
`ifdef MX25L4005
if (status_reg[5:2]==4'b0000) begin protected_area = 1'b0; end
else if (status_reg[5:2]==4'b0001) begin
if (sector[`SECTOR_ADDR - 1:4] == 7) begin protected_area = 1'b1; end else begin
protected_area = 1'b0; end end
else if (status_reg[5:2]==4'b0010) begin
if (sector[`SECTOR_ADDR - 1:4] >= 6 && sector[`SECTOR_ADDR - 1:4] <= 7) begin
protected_area = 1'b1; end else begin
protected_area = 1'b0; end end
else if (status_reg[5:2]==4'b0011) begin
if (sector[`SECTOR_ADDR - 1:4] >= 4 && sector[`SECTOR_ADDR - 1:4] <= 7) begin
protected_area = 1'b1; end else begin
protected_area = 1'b0;
end end
else if (status_reg[5:2]==4'b0100) begin protected_area = 1'b1; end
else if (status_reg[5:2]==4'b0101) begin protected_area = 1'b1; end
else if (status_reg[5:2]==4'b0110) begin protected_area = 1'b1; end
else if (status_reg[5:2]==4'b0111) begin protected_area = 1'b1; end else begin
protected_area = 1'b1; end `else
`ifdef MX25L1605A
if (status_reg[5:2]==4'b0000) begin protected_area = 1'b0; end
else if (status_reg[5:2]==4'b0001) begin
if (sector[`SECTOR_ADDR - 1:4] == 31) begin protected_area = 1'b1; end else begin
protected_area = 1'b0; end end
else if (status_reg[5:2]==4'b0010) begin
if (sector[`SECTOR_ADDR - 1:4] >= 30 && sector[`SECTOR_ADDR - 1:4] <= 31) begin
protected_area = 1'b1; end else begin
protected_area = 1'b0; end end
else if (status_reg[5:2]==4'b0011) begin
if (sector[`SECTOR_ADDR - 1:4] >= 28 && sector[`SECTOR_ADDR - 1:4] <= 31) begin
protected_area = 1'b1; end
else begin
protected_area = 1'b0; end end
else if (status_reg[5:2]==4'b0100) begin
if (sector[`SECTOR_ADDR - 1:4] >= 24 && sector[`SECTOR_ADDR - 1:4] <= 31) begin
protected_area = 1'b1; end else begin
protected_area = 1'b0; end end
else if (status_reg[5:2]==4'b0101) begin if (sector[`SECTOR_ADDR - 1:4] >= 16 && sector[`SECTOR_ADDR - 1:4] <= 31) begin
protected_area = 1'b1; end else begin protected_area = 1'b0; end end
else if (status_reg[5:2]==4'b0110) begin protected_area = 1'b1; end
else if (status_reg[5:2]==4'b0111) begin protected_area = 1'b1; end else begin
protected_area = 1'b1; end `endif `endif end
endfunction
////////////////////////////////////////////////////////////////////// // AC Timing Check Section
////////////////////////////////////////////////////////////////////// specify
//====================================================== // AC Timing Parameter
//====================================================== specparam tCYC = 14, // Clock Cycle Time [ns]
tCH = 7, // Clock High Time (min) [ns] tCL = 7, // Clock Low Time (min) [ns]
tSLCH = 5, // CS Lead Clock Time (min) [ns] tCHSL = 5, // CS Lag Clock Time (min) [ns] tSHSL = 100, // CS High Time (min) [ns] tDVCH = 2, // SI Setup Time (min) [ns] tCHDX = 5; // SI Hold Time (min) [ns]
//====================================================== // Timing Check
//====================================================== $period( posedge SCLK , tCYC ); // SCLK _/~ -> _/~ $period( negedge SCLK , tCYC ); // SCLK ~\\_ -> ~\\_ $width ( posedge SCLK , tCH ); // SCLK _/~~\\_ $width ( negedge SCLK , tCL ); // SCLK ~\\__/~ $width ( posedge CS , tSHSL ); // CS _/~\\_
$setuphold( posedge SCLK &&& ~CS, SI, tDVCH, tCHDX ); $setup ( CS, posedge SCLK &&& ~CS, tSLCH ); $hold ( negedge SCLK &&& ~CS, CS, tCHSL );
endspecify endmodule