温州大学瓯江学院本科毕业论文
附录Ⅱ 元器件清单
器件名称 Spartan-3E 芯片 规格 1K 10K 数量 1 5 15 15 15 8 若干 1 4 四位7段LED数码管 三极管 电阻 电阻 按键 杜邦线 蜂鸣器 LED灯
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温州大学瓯江学院本科毕业论文
附录Ⅲ 源程序清单
判断电路
--------------------------------------------------------------------------------- library IEEE; --库说明 use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;
--use UNISIM.VComponents.all;
entity panduandianlu is
Port ( CLR : in STD_LOGIC; ----复位信号 EN : in STD_LOGIC; ----抢答使能信号 A,B,C,D : in STD_LOGIC; ----抢答按钮
LEDA : out STD_LOGIC; ----抢答成功指示灯 LEDB : out STD_LOGIC; LEDC : out STD_LOGIC; LEDD : out STD_LOGIC;
FALSE : out STD_LOGIC_VECTOR (3 downto 0); ----抢答提前警报
Q : out STD_LOGIC_VECTOR (3 downto 0)); ----抢答成功组显示
end panduandianlu;
architecture rtl of panduandianlu is
signal tmp:std_logic_vector(3 downto 0);
signal tag:std_logic; ----设置锁存标志位 begin
tmp<=a&b&c&d;
process(CLR,en,a,b,c,d,tmp) ----启动进程
begin
if clr='1'then ----电路清零 q<=\ LEDA<='0'; LEDB<='0'; LEDC<='0'; LEDD<='0';
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温州大学瓯江学院本科毕业论文
FALSE<=\ TAG<='0';
ELSIF EN='0'THEN ----抢答提前报警
IF A='1'THEN FALSE(3)<='1'; END IF; IF B='1'THEN FALSE(2)<='1'; END IF; IF C='1'THEN FALSE(1)<='1'; END IF; IF D='1'THEN FALSE(0)<='1'; END IF;
ELSE FALSE<=\ IF TAG='0'THEN 功者出现 IF TMP=\ LEDA<='1'; 示灯亮 LEDB<='0'; LEDC<='0'; LEDD<='0'; Q<=\ 成功 TAG<='1'; ELSIF TMP=\ LEDA<='0'; LEDB<='1'; LEDC<='0'; LEDD<='0'; Q<=\ TAG<='1'; ELSIF TMP=\ LEDA<='0';
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----抢答开始 ----报警信号清零 ----尚未有抢答成----A抢答成功 ----A抢答成功指----显示A抢答 ----锁存此状态 温州大学瓯江学院本科毕业论文
LEDB<='0'; LEDC<='1'; LEDD<='0'; Q<=\ TAG<='1'; ELSIF TMP=\ LEDA<='0'; LEDB<='0'; LEDC<='0'; LEDD<='1'; Q<=\ TAG<='1'; END IF; END IF; END IF;
END PROCESS; end rtl;
计分电路
library IEEE; ----库说明 use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;
--use UNISIM.VComponents.all;
entity jifen is
Port ( add : in STD_LOGIC; ----加分信号 clear: in std_logic; ----复位清零信号
chos : in STD_LOGIC_VECTOR (3 downto 0); ----对应抢答组信号
a2,a1,a0 : out STD_LOGIC_VECTOR (3 downto 0); ----各组计分信号
b2,b1,b0 : out STD_LOGIC_VECTOR (3 downto 0); c2,c1,c0 : out STD_LOGIC_VECTOR (3 downto 0); d2,d1,d0 : out STD_LOGIC_VECTOR (3 downto 0) ); end jifen;
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温州大学瓯江学院本科毕业论文
architecture rtl of jifen is SIGNAL
A11,A22,A33,B11,B22,B33,C11,C22,C33,D11,D22,D33:STD_LOGIC_VECTOR(3 downto 0); ----定义变量 begin
A0<=A11; A1<=A22; A2<=A33; B0<=B11; B1<=B22; B2<=B33; C0<=C11; C1<=C22; C2<=C33; D0<=D11; D1<=D22; D2<=D33;
PROCESS(ADD,CHOS,clear)
BEGIN
if clear='1' then A11<=\ A22<=\ A33<=\ B11<=\ B22<=\ B33<=\ C11<=\ C22<=\ C33<=\ D11<=\ D22<=\ D33<=\ elsIF ADD' EVENT AND ADD='1'THEN 升沿有效
IF CHOS=\ 10分 IF (A22=\ A22<=\ IF (A33=\ THEN - 26 -
----启动进程 ----电路清零 ----加分信号上 ----A组答对，加 ----十位为9 ----十位清零 ----百位为9