温州大学瓯江学院本科毕业论文
A33<=\ ----百位清零 ELSE A33<=A33+'1'; ----否则百位加1 END IF; ELSE A22<=A22+'1'; ----否则十位加1 END IF; end if;
IF CHOS=\ IF (B22=\ B22<=\ IF (B33=\ THEN B33<=\ ELSE B33<=B33+'1'; END IF; ELSE B22<=B22+'1'; END IF; end if; IF CHOS=\ IF (C22=\ C22<=\ IF (C33=\ THEN C33<=\ ELSE C33<=C33+'1'; END IF; ELSE C22<=C22+'1'; END IF; end if; IF CHOS=\ IF (D22=\ D22<=\ IF (D33=\ THEN D33<=\ ELSE D33<=D33+'1'; END IF; ELSE
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温州大学瓯江学院本科毕业论文
D22<=D22+'1'; END IF; END IF; end if;
END PROCESS; end rtl;
七段码显示电路
----------------------------------------------------------------------------------
library IEEE; ----库说明 use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;
--use UNISIM.VComponents.all;
entity xianshidianlu is
Port ( DIN : in STD_LOGIC_VECTOR (3 downto 0); ----输入信号 DOTU : out STD_LOGIC_VECTOR (6 downto 0)); ----译码显示输出信号
end xianshidianlu;
architecture rtl of xianshidianlu is begin
PROCESS(DIN) ----启动进程 BEGIN
CASE DIN IS ----译码 WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN\ WHEN OTHERS=>DOTU<=\ END CASE; END PROCESS;
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温州大学瓯江学院本科毕业论文
end rtl;
倒计时电路
----------------------------------------------------------------------------------
library IEEE; ----库说明 use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;
--use UNISIM.VComponents.all;
entity daojishi is
Port ( clk,clr,rst : in STD_LOGIC; ----clk时钟信号，clr复位信号，rst计时开始中止信号
m : out STD_LOGIC; ----声音输出信号
high,low : out STD_LOGIC_VECTOR (3 downto 0)); ----计时输出信号
end daojishi;
architecture rtl of daojishi is
signal hh:std_logic_vector(3 downto 0); ----定义变量 signal ll:std_logic_vector(3 downto 0); begin
process(clk,clr,rst,hh,ll) ----启动进程 begin
if clr='1' then ll<=\ ----电路清零 elsif clk'event and clk='1' then ----时钟上升沿有效 if rst='1' then ll<=ll-1; ----rst高电平，个位减1 if ll=\ ----当个位为0时，个位回到9，十位减1
if hh=\ ----直到个位十位为0 m<='1'; ----计时到则触发声音信号 hh<=\ ll<=\ end if; end if; end if; end if;
high<=ll;low<=hh; end process;
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温州大学瓯江学院本科毕业论文
end rtl;
位选选择
---------------------------------------------------------------------------------- library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dynamic is
Port ( clk : in std_logic; reset: in std_logic; din1 : in std_logic_vector(3 downto 0); 进制数据
din2 : in std_logic_vector(3 downto 0); din3 : in std_logic_vector(3 downto 0); din4 : in std_logic_vector(3 downto 0); din5 : in std_logic_vector(3 downto 0); din6 : in std_logic_vector(3 downto 0); din7 : in std_logic_vector(3 downto 0); din8 : in std_logic_vector(3 downto 0); din9 : in std_logic_vector(3 downto 0); din10 : in std_logic_vector(3 downto 0); din11 : in std_logic_vector(3 downto 0); din12 : in std_logic_vector(3 downto 0); din13 : in std_logic_vector(3 downto 0); din14 : in std_logic_vector(3 downto 0); din15 : in std_logic_vector(3 downto 0);
shift: out std_logic_vector(14 downto 0); bus4 : out std_logic_vector(3 downto 0)); end dynamic;
architecture Behavioral of dynamic is
signal scan_clk:std_logic_vector(3 downto 0); begin
process(clk,scan_clk,reset) begin
if reset='1' then scan_clk<=\
elsif clk'event and clk='1'then scan_clk<=scan_clk+1; if(scan_clk=12) then scan_clk<=\
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--译码后的数据信号1（4位2 --译码后的数据信号2 --译码后的数据信号3 --位选信号 --数据信号 --分频进程 温州大学瓯江学院本科毕业论文
end if; end if; end process;
process(scan_clk,din1,din2,din3,din4,din5,din6,din7,din8,din9,din10,din11,din12,din13,din14,din15) ----启动进程 begin
case scan_clk is when \ bus4<=din1;
shift<=\ when \ bus4<=din2;
shift<=\ when \ bus4<=din3;
shift<=\ when \ bus4<=din4;
shift<=\ when \ bus4<=din5;
shift<=\ when \ bus4<=din6;
shift<=\ when \ bus4<=din7;
shift<=\ when \ bus4<=din8;
shift<=\ when \ bus4<=din9;
shift<=\ when \ bus4<=din10;
shift<=\ when \ bus4<=din11;
shift<=\ when \ bus4<=din12;
shift<=\
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