温州大学瓯江学院本科毕业论文
when \ bus4<=din13;
shift<=\ when \ bus4<=din14;
shift<=\ when \ bus4<=din15;
shift<=\
when others=> bus4<=\ end case; end process; end Behavioral;
分频1ms
---------------------------------------------------------------------------------- library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM;
--use UNISIM.VComponents.all;
entity f01ms is
Port (CLK:in std_logic;
architecture Behavioral of f01ms is signal a:integer range 0 to 5000; begin
process(CLK) begin
if(CLK'event and CLK='1') then if a=4999 then
a<=0;
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CP:out std_logic);
end f01ms;
温州大学瓯江学院本科毕业论文
else a<=a+1; end if;
case a is
when 0 to 2499=>CP<='1'; when 2500 to 4999=>CP<='0'; when others =>CP<='Z'; end case; end if;
end process;
end Behavioral; 分频1S
---------------------------------------------------------------------------------- library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM;
--use UNISIM.VComponents.all;
entity fpq1S is
Port (CLK:in std_logic;
architecture Behavioral of fpq1S is signal count:integer range 0 to 50000000; begin
process(CLK)
begin
if(CLK'event and CLK='1') then if count=49999999 then
- 33 -
CP:out std_logic);
end fpq1S;
温州大学瓯江学院本科毕业论文
count<=0;
else
count<=count+1; end if;
case count is
when 0 to 24999999=>CP<='1'; when 25000000 to 49999999=>CP<='0'; when others =>CP<='Z'; end case;
end if;
end process;
end Behavioral;
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