s3c6410寄存器定义

//init.s

PRESERVE8

;*************************************************************************************/

IMPORT Main IMPORT ledisr

AREA Init,CODE,READONLY ENTRY

;--------------------------------------------------------------- reset

ldr sp,=0X50100000 msr cpsr_c,#0xd2 ldr sp,=0X50200000 msr cpsr_c,#0xdf ldr sp,=0X50300000

;开启中断VECT

mrc p15,0,r0,c1,c0,0 orr r0,r0,#(1<<24) mcr p15,0,r0,c1,c0,0

;允许中断,开启CPU总中断

MRS R0, CPSR ;将CPSR保存至R0寄存器中 BIC R0, R0, #0x80 ;R0 = R0 & ~0x80,清除中断位 MSR CPSR_c, R0

bl Main END

//main.c

//main.c

#include \

#define keycon GPNCON_REG #define key GPNDAT_REG

#define ledcon GPMCON_REG

#define led GPMDAT_REG // gpm0~3

void delay(void);

void ledisr(void) __irq ;

void delay(void) {

unsigned int i = 20000000; while(i--); }

void Main(void) {

ledcon |= 0xf; led = 0;

keycon &= 1<<2; keycon |= 0x2;

EINT0CON0 &= 1<<3; EINT0CON0 |=0x6;

EINT0MASK &=~(0x1);

VIC0VECTADDR[0] = (int)ledisr; VIC0INTSELECT &=~(1<<0); VIC0INTENABLE |= 1<<0;

while(1)

{

led |= 0xf; } }

void ledisr(void) __irq {

led &= ~(0xf); delay();

EINT0PEND = 1; VIC0ADDRESS = 0; }

//s3c6410.h /* form

\\Linux-3.0.1\%uboot_sourcecode\%uboot1.1.6-2012-09-25\%uboot1.1.6\\include */

#ifndef __S3C6410_H__ #define __S3C6410_H__

#ifndef CONFIG_S3C6410

#define CONFIG_S3C6410 1 #endif

#define S3C64XX_UART_CHANNELS 3 #define S3C64XX_SPI_CHANNELS 2

#define __REG(x) (*(volatile unsigned*)(x)) // copy from hardware.h

#ifndef __ASSEMBLY__ typedef enum { S3C64XX_UART0, S3C64XX_UART1, S3C64XX_UART2, S3C64XX_UART3, } S3C64XX_UARTS_NR;

//#include #endif

#define BIT0 0x00000001 #define BIT1 0x00000002 #define BIT2 0x00000004 #define BIT3 0x00000008 #define BIT4 0x00000010 #define BIT5 0x00000020 #define BIT6 0x00000040 #define BIT7 0x00000080 #define BIT8 0x00000100 #define BIT9 0x00000200 #define BIT10 0x00000400 #define BIT11 0x00000800 #define BIT12 0x00001000 #define BIT13 0x00002000 #define BIT14 0x00004000 #define BIT15 0x00008000 #define BIT16 0x00010000 #define BIT17 0x00020000 #define BIT18 0x00040000 #define BIT19 0x00080000 #define BIT20 0x00100000 #define BIT21 0x00200000 #define BIT22 0x00400000 #define BIT23 0x00800000 #define BIT24 0x01000000 #define BIT25 0x02000000 #define BIT26 0x04000000 #define BIT27 0x08000000 #define BIT28 0x10000000 #define BIT29 0x20000000 #define BIT30 0x40000000 #define BIT31 0x80000000

#define ROM_BASE0 0x00000000 /* base address of rom bank 0 */ #define ROM_BASE1 0x04000000 /* base address of rom bank 1 */ #define DRAM_BASE0 0x40000000 /* base address of dram bank 0 */ #define DRAM_BASE1 0x50000000 /* base address of dram bank 1 */

/* S3C6400 device base addresses */

#define ELFIN_DMA_BASE 0x75000000 #define ELFIN_LCD_BASE 0x77100000 #define ELFIN_USB_HOST_BASE 0x74300000 #define ELFIN_I2C_BASE 0x7f004000 #define ELFIN_I2S_BASE 0x7f002000 #define ELFIN_ADC_BASE 0x7e00b000 #define ELFIN_SPI_BASE 0x7f00b000 #define ELFIN_HSMMC_0_BASE 0x7c200000 #define ELFIN_HSMMC_1_BASE 0x7c300000 #define ELFIN_HSMMC_2_BASE 0x7c400000

#define ELFIN_CLOCK_POWER_BASE 0x7e00f000

/* Clock & Power Controller for mDirac3*/ #define APLL_LOCK_OFFSET 0x00 #define MPLL_LOCK_OFFSET 0x04 #define EPLL_LOCK_OFFSET 0x08 #define APLL_CON_OFFSET 0x0C #define MPLL_CON_OFFSET 0x10 #define EPLL_CON0_OFFSET 0x14 #define EPLL_CON1_OFFSET 0x18 #define CLK_SRC_OFFSET 0x1C #define CLK_DIV0_OFFSET 0x20 #define CLK_DIV1_OFFSET 0x24 #define CLK_DIV2_OFFSET 0x28 #define CLK_OUT_OFFSET 0x2C #define HCLK_GATE_OFFSET 0x30 #define PCLK_GATE_OFFSET 0x34 #define SCLK_GATE_OFFSET 0x38

#define AHB_CON0_OFFSET 0x100 #define AHB_CON1_OFFSET 0x104 #define AHB_CON2_OFFSET 0x108 #define SELECT_DMA_OFFSET 0x110 #define SW_RST_OFFSET 0x114 #define SYS_ID_OFFSET 0x118 #define MEM_SYS_CFG_OFFSET 0x120 #define QOS_OVERRIDE0_OFFSET 0x124 #define QOS_OVERRIDE1_OFFSET 0x128 #define MEM_CFG_STAT_OFFSET 0x12C #define PWR_CFG_OFFSET 0x804 #define EINT_MASK_OFFSET 0x808 #define NOR_CFG_OFFSET 0x810 #define STOP_CFG_OFFSET 0x814 #define SLEEP_CFG_OFFSET 0x818