#define ONENAND_SYS_CFG1_BRL_8 (0 << 12) #define ONENAND_SYS_CFG1_BRL_SHIFT (12) #define ONENAND_SYS_CFG1_BL_32 (4 << 9) #define ONENAND_SYS_CFG1_BL_16 (3 << 9) #define ONENAND_SYS_CFG1_BL_8 (2 << 9) #define ONENAND_SYS_CFG1_BL_4 (1 << 9) #define ONENAND_SYS_CFG1_BL_CONT (0 << 9) #define ONENAND_SYS_CFG1_BL_SHIFT (9)
#define ONENAND_SYS_CFG1_NO_ECC (1 << 8) #define ONENAND_SYS_CFG1_RDY (1 << 7) #define ONENAND_SYS_CFG1_INT (1 << 6) #define ONENAND_SYS_CFG1_IOBE (1 << 5) #define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) /*
* Controller Status Register F240h (R) */
#define ONENAND_CTRL_ONGO (1 << 15) #define ONENAND_CTRL_LOCK (1 << 14) #define ONENAND_CTRL_LOAD (1 << 13) #define ONENAND_CTRL_PROGRAM (1 << 12) #define ONENAND_CTRL_ERASE (1 << 11) #define ONENAND_CTRL_ERROR (1 << 10) #define ONENAND_CTRL_RSTB (1 << 7) #define ONENAND_CTRL_OTP_L (1 << 6) #define ONENAND_CTRL_OTP_BL (1 << 5) /*
* Interrupt Status Register F241h (R) */
#define ONENAND_INT_MASTER (1 << 15) #define ONENAND_INT_READ (1 << 7) #define ONENAND_INT_WRITE (1 << 6) #define ONENAND_INT_ERASE (1 << 5) #define ONENAND_INT_RESET (1 << 4) #define ONENAND_INT_CLEAR (0 << 0) /*
* NAND Flash Write Protection Status Register F24Eh (R) */
#define ONENAND_WP_US (1 << 2) #define ONENAND_WP_LS (1 << 1) #define ONENAND_WP_LTS (1 << 0)
/*
* ECC Status Register FF00h (R) */
#define ONENAND_ECC_1BIT (1 << 0) #define ONENAND_ECC_1BIT_ALL (0x5555) #define ONENAND_ECC_2BIT (1 << 1) #define ONENAND_ECC_2BIT_ALL (0xAAAA) /*
* One-Time Programmable (OTP) */
#define ONENAND_OTP_LOCK_OFFSET (14)
/************************************************************* * End of OneNAND Controller
*************************************************************/ /*
* Interrupt */
#define ELFIN_VIC0_BASE_ADDR (0x71200000) #define ELFIN_VIC1_BASE_ADDR (0x71300000) #define oINTMOD (0x0C) // VIC INT SELECT (IRQ or FIQ)
#define oINTUNMSK (0x10) // VIC INT EN (Unmask by writing 1) #define oINTMSK (0x14) // VIC INT EN CLEAR (Mask by writing 1) #define oINTSUBMSK (0x1C) // VIC SOFT INT CLEAR #define oVECTADDR (0xF00) // VIC ADDRESS /*
* Watchdog timer */
#define ELFIN_WATCHDOG_BASE 0x7E004000
#define WTCON_REG __REG(0x7E004004) #define WTDAT_REG __REG(0x7E004008) #define WTCNT_REG __REG(0x7E00400C) /*
* UART
*/
#define ELFIN_UART_BASE 0x7F005000
#define ELFIN_UART0_OFFSET 0x0000 #define ELFIN_UART1_OFFSET 0x0400 #define ELFIN_UART2_OFFSET 0x0800 #define ELFIN_UART3_OFFSET 0x0c00
#ifdef CONFIG_SERIAL1
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET) #elif defined(CONFIG_SERIAL2)
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET) #elif defined(CONFIG_SERIAL3)
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET) #elif defined(CONFIG_SERIAL4)
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART3_OFFSET) #else
#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET) #endif
#define ULCON_OFFSET 0x00 #define UCON_OFFSET 0x04 #define UFCON_OFFSET 0x08 #define UMCON_OFFSET 0x0C #define UTRSTAT_OFFSET 0x10 #define UERSTAT_OFFSET 0x14 #define UFSTAT_OFFSET 0x18 #define UMSTAT_OFFSET 0x1C #define UTXH_OFFSET 0x20 #define URXH_OFFSET 0x24 #define UBRDIV_OFFSET 0x28 #define UDIVSLOT_OFFSET 0x2C #define UINTP_OFFSET 0x30 #define UINTSP_OFFSET 0x34 #define UINTM_OFFSET 0x38
#define ULCON0_REG __REG(0x7F005000) #define UCON0_REG __REG(0x7F005004) #define UFCON0_REG __REG(0x7F005008) #define UMCON0_REG __REG(0x7F00500C) #define UTRSTAT0_REG __REG(0x7F005010) #define UERSTAT0_REG __REG(0x7F005014) #define UFSTAT0_REG __REG(0x7F005018) #define UMSTAT0_REG __REG(0x7F00501c)
#define UTXH0_REG __REG(0x7F005020) #define URXH0_REG __REG(0x7F005024) #define UBRDIV0_REG __REG(0x7F005028) #define UDIVSLOT0_REG __REG(0x7F00502c) #define UINTP0_REG __REG(0x7F005030) #define UINTSP0_REG __REG(0x7F005034) #define UINTM0_REG __REG(0x7F005038)
#define ULCON1_REG __REG(0x7F005400) #define UCON1_REG __REG(0x7F005404) #define UFCON1_REG __REG(0x7F005408) #define UMCON1_REG __REG(0x7F00540C) #define UTRSTAT1_REG __REG(0x7F005410) #define UERSTAT1_REG __REG(0x7F005414) #define UFSTAT1_REG __REG(0x7F005418) #define UMSTAT1_REG __REG(0x7F00541c) #define UTXH1_REG __REG(0x7F005420) #define URXH1_REG __REG(0x7F005424) #define UBRDIV1_REG __REG(0x7F005428) #define UDIVSLOT1_REG __REG(0x7F00542c) #define UINTP1_REG __REG(0x7F005430) #define UINTSP1_REG __REG(0x7F005434) #define UINTM1_REG __REG(0x7F005438)
#define UTRSTAT_TX_EMPTY BIT2 #define UTRSTAT_RX_READY BIT0 #define UART_ERR_MASK 0xF /*
* PWM timer */
#define ELFIN_TIMER_BASE 0x7F006000
#define TCFG0_REG __REG(0x7F006000) #define TCFG1_REG __REG(0x7F006004) #define TCON_REG __REG(0x7F006008) #define TCNTB0_REG __REG(0x7F00600c) #define TCMPB0_REG __REG(0x7F006010) #define TCNTO0_REG __REG(0x7F006014) #define TCNTB1_REG __REG(0x7F006018) #define TCMPB1_REG __REG(0x7F00601c) #define TCNTO1_REG __REG(0x7F006020) #define TCNTB2_REG __REG(0x7F006024)
#define TCMPB2_REG __REG(0x7F006028) #define TCNTO2_REG __REG(0x7F00602c) #define TCNTB3_REG __REG(0x7F006030) #define TCMPB3_REG __REG(0x7F006034) #define TCNTO3_REG __REG(0x7F006038) #define TCNTB4_REG __REG(0x7F00603c) #define TCNTO4_REG __REG(0x7F006040)
/* Fields */
#define fTCFG0_DZONE Fld(8,16) /* the dead zone length (= timer 0) */
#define fTCFG0_PRE1 Fld(8,8) /* prescaler value for time 2,3,4 */ #define fTCFG0_PRE0 Fld(8,0) /* prescaler value for time 0,1 */ #define fTCFG1_MUX4 Fld(4,16) /* bits */
#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) #define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) #define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) #define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ #define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ #define COUNT_4_ON (TCON_4_ONOFF*1) #define COUNT_4_OFF (TCON_4_ONOFF*0) #define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ #define TIMER3_ATLOAD_ON (TCON_3_AUTO*1)
#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ #define TIMER3_IVT_ON (TCON_3_INVERT*1)
#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ #define TIMER3_MANUP (TCON_3_MAN*1)
#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ #define TIMER3_ON (TCON_3_ONOFF*1)
#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) /* macros */
#define GET_PRESCALE_TIMER4(x) FExtr((x), fTCFG0_PRE1) #define GET_DIVIDER_TIMER4(x) FExtr((x), fTCFG1_MUX4) /*
* RTC Controller */
#define ELFIN_RTC_BASE 0x7e005000