#define INDEX_DMC_T_MRD (0x1C) #define INDEX_DMC_T_RAS (0x20) #define INDEX_DMC_T_RC (0x24) #define INDEX_DMC_T_RCD (0x28) #define INDEX_DMC_T_RFC (0x2C) #define INDEX_DMC_T_RP (0x30) #define INDEX_DMC_T_RRD (0x34) #define INDEX_DMC_T_WR (0x38) #define INDEX_DMC_T_WTR (0x3C) #define INDEX_DMC_T_XP (0x40) #define INDEX_DMC_T_XSR (0x44) #define INDEX_DMC_T_ESR (0x48) #define INDEX_DMC_MEMORY_CFG2 (0x4C) #define INDEX_DMC_CHIP_0_CFG (0x200) #define INDEX_DMC_CHIP_1_CFG (0x204) #define INDEX_DMC_CHIP_2_CFG (0x208) #define INDEX_DMC_CHIP_3_CFG (0x20C) #define INDEX_DMC_USER_STATUS (0x300) #define INDEX_DMC_USER_CONFIG (0x304) /*
* Memory Chip direct command */
#define DMC_NOP0 0x0c0000 #define DMC_NOP1 0x1c0000
#define DMC_PA0 0x000000 //Precharge all #define DMC_PA1 0x100000
#define DMC_AR0 0x040000 //Autorefresh #define DMC_AR1 0x140000 #define DMC_SDR_MR0 0x080032 //MRS, CAS 3, Burst Length 4 #define DMC_SDR_MR1 0x180032 #define DMC_DDR_MR0 0x080162 #define DMC_DDR_MR1 0x180162
#define DMC_mDDR_MR0 0x080032 //CAS 3, Burst Length 4 #define DMC_mDDR_MR1 0x180032
#define DMC_mSDR_EMR0 0x0a0000 //EMRS, DS:Full, PASR:Full Array #define DMC_mSDR_EMR1 0x1a0000 #define DMC_DDR_EMR0 0x090000 #define DMC_DDR_EMR1 0x190000
#define DMC_mDDR_EMR0 0x0a0000 // DS:Full, PASR:Full Array #define DMC_mDDR_EMR1 0x1a0000
/****************************************************************
Definitions for memory configuration Set memory configuration
active_chips = 1'b0 (1 chip)
qos_master_chip = 3'b000(ARID[3:0]) memory burst = 3'b010(burst 4)
stop_mem_clock = 1'b0(disable dynamical stop)
auto_power_down = 1'b0(disable auto power-down mode)
power_down_prd = 6'b00_0000(0 cycle for auto power-down) ap_bit = 1'b0 (bit position of auto-precharge is 10) row_bits = 3'b010(# row address 13) column_bits = 3'b010(# column address 10 )
Set user configuration
2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
Set chip select for chip [n]
row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
******************************************************************/ /*
* HS MMC Interface */
#define ELFIN_HSMMC_BASE 0x7C200000
#define HM_SYSAD (0x00) #define HM_BLKSIZE (0x04) #define HM_BLKCNT (0x06) #define HM_ARGUMENT (0x08) #define HM_TRNMOD (0x0c) #define HM_CMDREG (0x0e) #define HM_RSPREG0 (0x10) #define HM_RSPREG1 (0x14) #define HM_RSPREG2 (0x18) #define HM_RSPREG3 (0x1c) #define HM_BDATA (0x20) #define HM_PRNSTS (0x24) #define HM_HOSTCTL (0x28) #define HM_PWRCON (0x29) #define HM_BLKGAP (0x2a) #define HM_WAKCON (0x2b) #define HM_CLKCON (0x2c) #define HM_TIMEOUTCON (0x2e) #define HM_SWRST (0x2f)
#define HM_NORINTSTS (0x30) #define HM_ERRINTSTS (0x32) #define HM_NORINTSTSEN (0x34) #define HM_ERRINTSTSEN (0x36) #define HM_NORINTSIGEN (0x38) #define HM_ERRINTSIGEN (0x3a) #define HM_ACMD12ERRSTS (0x3c) #define HM_CAPAREG (0x40) #define HM_MAXCURR (0x48) #define HM_CONTROL2 (0x80) #define HM_CONTROL3 (0x84) #define HM_CONTROL4 (0x8c) #define HM_HCVER (0xfe) /*
* Nand flash controller */
#define ELFIN_NAND_BASE 0x70200000
#define NFCONF_OFFSET 0x00 #define NFCONT_OFFSET 0x04 #define NFCMMD_OFFSET 0x08 #define NFADDR_OFFSET 0x0c #define NFDATA_OFFSET 0x10
#define NFMECCDATA0_OFFSET 0x14 #define NFMECCDATA1_OFFSET 0x18 #define NFSECCDATA0_OFFSET 0x1c #define NFSBLK_OFFSET 0x20 #define NFEBLK_OFFSET 0x24 #define NFSTAT_OFFSET 0x28 #define NFESTAT0_OFFSET 0x2c #define NFESTAT1_OFFSET 0x30 #define NFMECC0_OFFSET 0x34 #define NFMECC1_OFFSET 0x38 #define NFSECC_OFFSET 0x3c #define NFMLCBITPT_OFFSET 0x40 #define NF8ECCERR0_OFFSET 0x44 #define NF8ECCERR1_OFFSET 0x48 #define NF8ECCERR2_OFFSET 0x4c #define NFM8ECC0_OFFSET 0x50 #define NFM8ECC1_OFFSET 0x54 #define NFM8ECC2_OFFSET 0x58 #define NFM8ECC3_OFFSET 0x5c #define NFMLC8BITPT0_OFFSET 0x60
#define NFMLC8BITPT1_OFFSET 0x64
#define NFCONF (ELFIN_NAND_BASE+NFCONF_OFFSET) #define NFCONT (ELFIN_NAND_BASE+NFCONT_OFFSET) #define NFCMMD (ELFIN_NAND_BASE+NFCMMD_OFFSET) #define NFADDR (ELFIN_NAND_BASE+NFADDR_OFFSET) #define NFDATA (ELFIN_NAND_BASE+NFDATA_OFFSET)
#define NFMECCDATA0 (ELFIN_NAND_BASE+NFMECCDATA0_OFFSET) #define NFMECCDATA1 (ELFIN_NAND_BASE+NFMECCDATA1_OFFSET) #define NFSECCDATA0 (ELFIN_NAND_BASE+NFSECCDATA0_OFFSET) #define NFSBLK (ELFIN_NAND_BASE+NFSBLK_OFFSET) #define NFEBLK (ELFIN_NAND_BASE+NFEBLK_OFFSET) #define NFSTAT (ELFIN_NAND_BASE+NFSTAT_OFFSET) #define NFESTAT0 (ELFIN_NAND_BASE+NFESTAT0_OFFSET) #define NFESTAT1 (ELFIN_NAND_BASE+NFESTAT1_OFFSET) #define NFMECC0 (ELFIN_NAND_BASE+NFMECC0_OFFSET) #define NFMECC1 (ELFIN_NAND_BASE+NFMECC1_OFFSET) #define NFSECC (ELFIN_NAND_BASE+NFSECC_OFFSET)
#define NFMLCBITPT (ELFIN_NAND_BASE+NFMLCBITPT_OFFSET) #define NF8ECCERR0 (ELFIN_NAND_BASE+NF8ECCERR0_OFFSET) #define NF8ECCERR1 (ELFIN_NAND_BASE+NF8ECCERR1_OFFSET) #define NF8ECCERR2 (ELFIN_NAND_BASE+NF8ECCERR2_OFFSET) #define NFM8ECC0 (ELFIN_NAND_BASE+NFM8ECC0_OFFSET) #define NFM8ECC1 (ELFIN_NAND_BASE+NFM8ECC1_OFFSET) #define NFM8ECC2 (ELFIN_NAND_BASE+NFM8ECC2_OFFSET) #define NFM8ECC3 (ELFIN_NAND_BASE+NFM8ECC3_OFFSET)
#define NFMLC8BITPT0 (ELFIN_NAND_BASE+NFMLC8BITPT0_OFFSET) #define NFMLC8BITPT1 (ELFIN_NAND_BASE+NFMLC8BITPT1_OFFSET)
#define NFCONF_REG __REG(ELFIN_NAND_BASE+NFCONF_OFFSET) #define NFCONT_REG __REG(ELFIN_NAND_BASE+NFCONT_OFFSET) #define NFCMD_REG __REG(ELFIN_NAND_BASE+NFCMMD_OFFSET)
#define NFADDR_REG __REG(ELFIN_NAND_BASE+NFADDR_OFFSET) #define NFDATA_REG __REG(ELFIN_NAND_BASE+NFDATA_OFFSET) #define NFDATA8_REG __REGb(ELFIN_NAND_BASE+NFDATA_OFFSET) #define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE+NFMECCDATA0_OFFSET) #define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE+NFMECCDATA1_OFFSET) #define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE+NFSECCDATA0_OFFSET) #define NFSBLK_REG __REG(ELFIN_NAND_BASE+NFSBLK_OFFSET) #define NFEBLK_REG __REG(ELFIN_NAND_BASE+NFEBLK_OFFSET) #define NFSTAT_REG __REG(ELFIN_NAND_BASE+NFSTAT_OFFSET) #define NFESTAT0_REG __REG(ELFIN_NAND_BASE+NFESTAT0_OFFSET) #define NFESTAT1_REG __REG(ELFIN_NAND_BASE+NFESTAT1_OFFSET) #define NFMECC0_REG __REG(ELFIN_NAND_BASE+NFMECC0_OFFSET)
#define NFMECC1_REG __REG(ELFIN_NAND_BASE+NFMECC1_OFFSET) #define NFSECC_REG __REG(ELFIN_NAND_BASE+NFSECC_OFFSET)
#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE+NFMLCBITPT_OFFSET)
#define NFCONF_ECC_MLC (1<<24)
#define NFCONF_ECC_1BIT (0<<23) #define NFCONF_ECC_4BIT (2<<23) #define NFCONF_ECC_8BIT (1<<23)
#define NFCONT_ECC_ENC (1<<18) #define NFCONT_WP (1<<16)
#define NFCONT_MECCLOCK (1<<7) #define NFCONT_SECCLOCK (1<<6) #define NFCONT_INITMECC (1<<5) #define NFCONT_INITSECC (1<<4)
#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) #define NFCONT_CS_ALT (1<<1) #define NFCONT_CS (1<<1) #define NFSTAT_ECCENCDONE (1<<7) #define NFSTAT_ECCDECDONE (1<<6) #define NFSTAT_RnB (1<<0)
#define NFESTAT0_ECCBUSY (1<<31)
/************************************************************* * OneNAND Controller
*************************************************************/ /*
* S3C6400 SFRs */
#define ONENAND_REG_MEM_CFG (0x000) #define ONENAND_REG_BURST_LEN (0x010) #define ONENAND_REG_MEM_RESET (0x020) #define ONENAND_REG_INT_ERR_STAT (0x030) #define ONENAND_REG_INT_ERR_MASK (0x040) #define ONENAND_REG_INT_ERR_ACK (0x050) #define ONENAND_REG_ECC_ERR_STAT (0x060) #define ONENAND_REG_MANUFACT_ID (0x070) #define ONENAND_REG_DEVICE_ID (0x080) #define ONENAND_REG_DATA_BUF_SIZE (0x090) #define ONENAND_REG_BOOT_BUF_SIZE (0x0A0)