#define OSC_FREQ_OFFSET 0x820 #define OSC_STABLE_OFFSET 0x824 #define PWR_STABLE_OFFSET 0x828 #define FPC_STABLE_OFFSET 0x82C #define MTC_STABLE_OFFSET 0x830 #define OTHERS_OFFSET 0x900 #define RST_STAT_OFFSET 0x904 #define WAKEUP_STAT_OFFSET 0x908 #define BLK_PWR_STAT_OFFSET 0x90C #define INF_REG0_OFFSET 0xA00 #define INF_REG1_OFFSET 0xA04 #define INF_REG2_OFFSET 0xA08 #define INF_REG3_OFFSET 0xA0C #define INF_REG4_OFFSET 0xA10 #define INF_REG5_OFFSET 0xA14 #define INF_REG6_OFFSET 0xA18 #define INF_REG7_OFFSET 0xA1C
#define OSC_CNT_VAL_OFFSET 0x824 #define PWR_CNT_VAL_OFFSET 0x828 #define FPC_CNT_VAL_OFFSET 0x82C #define MTC_CNT_VAL_OFFSET 0x830
#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+APLL_LOCK_OFFSET) #define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+MPLL_LOCK_OFFSET) #define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_LOCK_OFFSET) #define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE+APLL_CON_OFFSET) #define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE+MPLL_CON_OFFSET) #define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_CON0_OFFSET) #define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_CON1_OFFSET) #define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_SRC_OFFSET)
#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV0_OFFSET) #define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV1_OFFSET) #define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV2_OFFSET) #define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_OUT_OFFSET)
#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+HCLK_GATE_OFFSET) #define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+PCLK_GATE_OFFSET) #define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+SCLK_GATE_OFFSET) #define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON0_OFFSET) #define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON1_OFFSET) #define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON2_OFFSET) #define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE+SELECT_DMA_OFFSET) #define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE+SW_RST_OFFSET)
#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE+SYS_ID_OFFSET) #define MEM_SYS_CFG_REG
__REG(ELFIN_CLOCK_POWER_BASE+MEM_SYS_CFG_OFFSET) #define QOS_OVERRIDE0_REG
__REG(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE0_OFFSET) #define QOS_OVERRIDE1_REG
__REG(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE1_OFFSET) #define MEM_CFG_STAT_REG
__REG(ELFIN_CLOCK_POWER_BASE+MEM_CFG_STAT_OFFSET) #define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET)
#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET) #define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET)
#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+STOP_CFG_OFFSET) #define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET) #define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET) #define OSC_CNT_VAL_REG
__REG(ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET) #define PWR_CNT_VAL_REG
__REG(ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET) #define FPC_CNT_VAL_REG
__REG(ELFIN_CLOCK_POWER_BASE+FPC_CNT_VAL_OFFSET) #define MTC_CNT_VAL_REG
__REG(ELFIN_CLOCK_POWER_BASE+MTC_CNT_VAL_OFFSET)
#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE+OTHERS_OFFSET)
#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET) #define WAKEUP_STAT_REG
__REG(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET) #define BLK_PWR_STAT_REG
__REG(ELFIN_CLOCK_POWER_BASE+BLK_PWR_STAT_OFFSET)
#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET) #define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG1_OFFSET) #define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG2_OFFSET) #define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG3_OFFSET) #define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG4_OFFSET) #define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG5_OFFSET) #define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG6_OFFSET) #define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG7_OFFSET)
#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE+APLL_LOCK_OFFSET) #define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE+MPLL_LOCK_OFFSET) #define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE+EPLL_LOCK_OFFSET) #define APLL_CON (ELFIN_CLOCK_POWER_BASE+APLL_CON_OFFSET) #define MPLL_CON (ELFIN_CLOCK_POWER_BASE+MPLL_CON_OFFSET) #define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE+EPLL_CON0_OFFSET)
#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE+EPLL_CON1_OFFSET) #define CLK_SRC (ELFIN_CLOCK_POWER_BASE+CLK_SRC_OFFSET) #define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE+CLK_DIV0_OFFSET) #define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE+CLK_DIV1_OFFSET) #define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE+CLK_DIV2_OFFSET) #define CLK_OUT (ELFIN_CLOCK_POWER_BASE+CLK_OUT_OFFSET) #define HCLK_GATE (ELFIN_CLOCK_POWER_BASE+HCLK_GATE_OFFSET) #define PCLK_GATE (ELFIN_CLOCK_POWER_BASE+PCLK_GATE_OFFSET) #define SCLK_GATE (ELFIN_CLOCK_POWER_BASE+SCLK_GATE_OFFSET) #define AHB_CON0 (ELFIN_CLOCK_POWER_BASE+AHB_CON0_OFFSET) #define AHB_CON1 (ELFIN_CLOCK_POWER_BASE+AHB_CON1_OFFSET) #define AHB_CON2 (ELFIN_CLOCK_POWER_BASE+AHB_CON2_OFFSET) #define SELECT_DMA (ELFIN_CLOCK_POWER_BASE+SELECT_DMA_OFFSET) #define SW_RST (ELFIN_CLOCK_POWER_BASE+SW_RST_OFFSET) #define SYS_ID (ELFIN_CLOCK_POWER_BASE+SYS_ID_OFFSET) #define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE+MEM_SYS_CFG_OFFSET)
#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE0_OFFSET) #define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE1_OFFSET) #define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE+MEM_CFG_STAT_OFFSET) #define PWR_CFG (ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET) #define EINT_MASK (ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET) #define NOR_CFG (ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET) #define STOP_CFG (ELFIN_CLOCK_POWER_BASE+STOP_CFG_OFFSET) #define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET) #define OSC_FREQ (ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET) #define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET) #define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET) #define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+FPC_CNT_VAL_OFFSET) #define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+MTC_CNT_VAL_OFFSET) #define OTHERS (ELFIN_CLOCK_POWER_BASE+OTHERS_OFFSET) #define RST_STAT (ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET) #define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET)
#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE+BLK_PWR_STAT_OFFSET) #define INF_REG0 (ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET) #define INF_REG1 (ELFIN_CLOCK_POWER_BASE+INF_REG1_OFFSET) #define INF_REG2 (ELFIN_CLOCK_POWER_BASE+INF_REG2_OFFSET) #define INF_REG3 (ELFIN_CLOCK_POWER_BASE+INF_REG3_OFFSET) #define INF_REG4 (ELFIN_CLOCK_POWER_BASE+INF_REG4_OFFSET) #define INF_REG5 (ELFIN_CLOCK_POWER_BASE+INF_REG5_OFFSET) #define INF_REG6 (ELFIN_CLOCK_POWER_BASE+INF_REG6_OFFSET) #define INF_REG7 (ELFIN_CLOCK_POWER_BASE+INF_REG7_OFFSET) /*
* GPIO */
#define ELFIN_GPIO_BASE
#define GPACON_OFFSET #define GPADAT_OFFSET #define GPAPUD_OFFSET #define GPACONSLP_OFFSET #define GPAPUDSLP_OFFSET 0x7f008000
0x00 0x04 0x08 0x0C 0x10 #define GPBCON_OFFSET #define GPBDAT_OFFSET #define GPBPUD_OFFSET #define GPBCONSLP_OFFSET #define GPBPUDSLP_OFFSET #define GPCCON_OFFSET #define GPCDAT_OFFSET #define GPCPUD_OFFSET #define GPCCONSLP_OFFSET #define GPCPUDSLP_OFFSET #define GPDCON_OFFSET #define GPDDAT_OFFSET #define GPDPUD_OFFSET #define GPDCONSLP_OFFSET #define GPDPUDSLP_OFFSET #define GPECON_OFFSET #define GPEDAT_OFFSET #define GPEPUD_OFFSET #define GPECONSLP_OFFSET #define GPEPUDSLP_OFFSET #define GPFCON_OFFSET #define GPFDAT_OFFSET #define GPFPUD_OFFSET #define GPFCONSLP_OFFSET #define GPFPUDSLP_OFFSET #define GPGCON_OFFSET #define GPGDAT_OFFSET #define GPGPUD_OFFSET #define GPGCONSLP_OFFSET #define GPGPUDSLP_OFFSET #define GPHCON0_OFFSET #define GPHCON1_OFFSET #define GPHDAT_OFFSET #define GPHPUD_OFFSET #define GPHCONSLP_OFFSET
0x20 0x04 0x08 0x0C 0x30 0x40 0x44 0x48 0x4C 0x50 0x60 0x64 0x68 0x6C 0x70 0x80 0x84 0x88 0x8C 0x90 0xA0 0xA4 0xA8 0xAC 0xB0 0xC0 0xC4 0xC8 0xCC 0xD0 0xE0 0xE4 0xE8 0xEC 0xF0
#define GPHPUDSLP_OFFSET #define GPICON_OFFSET #define GPIDAT_OFFSET #define GPIPUD_OFFSET #define GPICONSLP_OFFSET #define GPIPUDSLP_OFFSET #define GPJCON_OFFSET #define GPJDAT_OFFSET #define GPJPUD_OFFSET 0xF4 0x100 0x104 0x108 0x10C 0x110 0x120 0x124 0x128 #define GPJCONSLP_OFFSET #define GPJPUDSLP_OFFSET #define SPCON_OFFSET #define MEM0DRVCON_OFFSET #define MEM1DRVCON_OFFSET #define GPKCON0_OFFSET #define GPKCON1_OFFSET #define GPKDAT_OFFSET #define GPKPUD_OFFSET #define GPLCON0_OFFSET #define GPLCON1_OFFSET #define GPLDAT_OFFSET #define GPLPUD_OFFSET #define GPMCON_OFFSET #define GPMDAT_OFFSET #define GPMPUD_OFFSET #define GPNCON_OFFSET #define GPNDAT_OFFSET #define GPNPUD_OFFSET #define GPOCON_OFFSET #define GPODAT_OFFSET #define GPOPUD_OFFSET #define GPOCONSLP_OFFSET #define GPOPUDSLP_OFFSET #define GPPCON_OFFSET #define GPPDAT_OFFSET #define GPPPUD_OFFSET #define GPPCONSLP_OFFSET #define GPPPUDSLP_OFFSET #define GPQCON_OFFSET #define GPQDAT_OFFSET #define GPQPUD_OFFSET #define GPQCONSLP_OFFSET #define GPQPUDSLP_OFFSET
0x12C 0x130 0x1A0 0x1D0 0x1D4 0x800 0x804 0x808 0x80C 0x810 0x814 0x818 0x81C 0x820 0x824 0x828 0x830 0x834 0x838 0x140 0x144 0x148 0x14C 0x150 0x160 0x164 0x168 0x16C 0x170 0x180 0x184 0x188 0x18C 0x190