#define RTCCON_REG __REG(0x7e005040) #define TICNT_REG __REG(0x7e005044) #define RTCALM_REG __REG(0x7e005050) #define ALMSEC_REG __REG(0x7e005054) #define ALMMIN_REG __REG(0x7e005058) #define ALMHOUR_REG __REG(0x7e00505c) #define ALMDATE_REG __REG(0x7e005060) #define ALMMON_REG __REG(0x7e005064) #define ALMYEAR_REG __REG(0x7e005068) #define BCDSEC_REG __REG(0x7e005070) #define BCDMIN_REG __REG(0x7e005074) #define BCDHOUR_REG __REG(0x7e005078) #define BCDDATE_REG __REG(0x7e00507c) #define BCDDAY_REG __REG(0x7e005080) #define BCDMON_REG __REG(0x7e005084) #define BCDYEAR_REG __REG(0x7e005088) /*
* USB2.0 HS OTG (Chapter 26) */
#define USBOTG_LINK_BASE (0x7C000000) #define USBOTG_PHY_BASE (0x7C100000)
/* Core Global Registers */
#define S3C_OTG_GOTGCTL (USBOTG_LINK_BASE + 0x000) /* OTG Control & Status */
#define S3C_OTG_GOTGINT (USBOTG_LINK_BASE + 0x004) /* OTG Interrupt */ #define S3C_OTG_GAHBCFG (USBOTG_LINK_BASE + 0x008) /* Core AHB Configuration */
#define S3C_OTG_GUSBCFG (USBOTG_LINK_BASE + 0x00C) /* Core USB Configuration */
#define S3C_OTG_GRSTCTL (USBOTG_LINK_BASE + 0x010) /* Core Reset */ #define S3C_OTG_GINTSTS (USBOTG_LINK_BASE + 0x014) /* Core Interrupt */
#define S3C_OTG_GINTMSK (USBOTG_LINK_BASE + 0x018) /* Core Interrupt Mask */
#define S3C_OTG_GRXSTSR (USBOTG_LINK_BASE + 0x01C) /* Receive Status Debug Read/Status Read */
#define S3C_OTG_GRXSTSP (USBOTG_LINK_BASE + 0x020) /* Receive Status Debug Pop/Status Pop */
#define S3C_OTG_GRXFSIZ (USBOTG_LINK_BASE + 0x024) /* Receive FIFO Size */
#define S3C_OTG_GNPTXFSIZ (USBOTG_LINK_BASE + 0x028) /* Non-Periodic Transmit FIFO Size */
#define S3C_OTG_GNPTXSTS (USBOTG_LINK_BASE + 0x02C) /* Non-Periodic Transmit FIFO/Queue Status */
#define S3C_OTG_HPTXFSIZ (USBOTG_LINK_BASE + 0x100) /* Host Periodic Transmit FIFO Size */
#define S3C_OTG_DPTXFSIZ1 (USBOTG_LINK_BASE + 0x104) /* Device Periodic Transmit FIFO-1 Size */
#define S3C_OTG_DPTXFSIZ2 (USBOTG_LINK_BASE + 0x108) /* Device Periodic Transmit FIFO-2 Size */
#define S3C_OTG_DPTXFSIZ3 (USBOTG_LINK_BASE + 0x10C) /* Device Periodic Transmit FIFO-3 Size */
#define S3C_OTG_DPTXFSIZ4 (USBOTG_LINK_BASE + 0x110) /* Device Periodic Transmit FIFO-4 Size */
#define S3C_OTG_DPTXFSIZ5 (USBOTG_LINK_BASE + 0x114) /* Device Periodic Transmit FIFO-5 Size */
#define S3C_OTG_DPTXFSIZ6 (USBOTG_LINK_BASE + 0x118) /* Device Periodic Transmit FIFO-6 Size */
#define S3C_OTG_DPTXFSIZ7 (USBOTG_LINK_BASE + 0x11C) /* Device Periodic Transmit FIFO-7 Size */
#define S3C_OTG_DPTXFSIZ8 (USBOTG_LINK_BASE + 0x120) /* Device Periodic Transmit FIFO-8 Size */
#define S3C_OTG_DPTXFSIZ9 (USBOTG_LINK_BASE + 0x124) /* Device Periodic Transmit FIFO-9 Size */
#define S3C_OTG_DPTXFSIZ10 (USBOTG_LINK_BASE + 0x128) /* Device Periodic Transmit FIFO-10 Size */
#define S3C_OTG_DPTXFSIZ11 (USBOTG_LINK_BASE + 0x12C) /* Device Periodic Transmit FIFO-11 Size */
#define S3C_OTG_DPTXFSIZ12 (USBOTG_LINK_BASE + 0x130) /* Device Periodic Transmit FIFO-12 Size */
#define S3C_OTG_DPTXFSIZ13 (USBOTG_LINK_BASE + 0x134) /* Device Periodic Transmit FIFO-13 Size */
#define S3C_OTG_DPTXFSIZ14 (USBOTG_LINK_BASE + 0x138) /* Device Periodic Transmit FIFO-14 Size */
#define S3C_OTG_DPTXFSIZ15 (USBOTG_LINK_BASE + 0x13C) /* Device Periodic Transmit FIFO-15 Size */
/* Host Global Registers */
#define S3C_OTG_HCFG (USBOTG_LINK_BASE + 0x400) /* Host Configuration */
#define S3C_OTG_HFIR (USBOTG_LINK_BASE + 0x404) /* Host Frame Interval */
#define S3C_OTG_HFNUM (USBOTG_LINK_BASE + 0x408) /* Host Frame Number/Frame Time Remaining */
#define S3C_OTG_HPTXSTS (USBOTG_LINK_BASE + 0x410) /* Host Periodic
Transmit FIFO/Queue Status */
#define S3C_OTG_HAINT (USBOTG_LINK_BASE + 0x414) /* Host All Channels Interrupt */
#define S3C_OTG_HAINTMSK (USBOTG_LINK_BASE + 0x418) /* Host All Channels Interrupt Mask */
/* Host Port Control & Status Registers */
#define S3C_OTG_HPRT (USBOTG_LINK_BASE + 0x440) /* Host Port Control & Status */
/* Host Channel-Specific Registers */
#define S3C_OTG_HCCHAR0 (USBOTG_LINK_BASE + 0x500) /* Host Channel-0 Characteristics */
#define S3C_OTG_HCSPLT0 (USBOTG_LINK_BASE + 0x504) /* Host Channel-0 Split Control */
#define S3C_OTG_HCINT0 (USBOTG_LINK_BASE + 0x508) /* Host Channel-0 Interrupt */
#define S3C_OTG_HCINTMSK0 (USBOTG_LINK_BASE + 0x50C) /* Host Channel-0 Interrupt Mask */
#define S3C_OTG_HCTSIZ0 (USBOTG_LINK_BASE + 0x510) /* Host Channel-0 Transfer Size */
#define S3C_OTG_HCDMA0 (USBOTG_LINK_BASE + 0x514) /* Host Channel-0 DMA Address */
/* Device Global Registers */
#define S3C_OTG_DCFG (USBOTG_LINK_BASE + 0x800) /* Device Configuration */
#define S3C_OTG_DCTL (USBOTG_LINK_BASE + 0x804) /* Device Control */ #define S3C_OTG_DSTS (USBOTG_LINK_BASE + 0x808) /* Device Status */ #define S3C_OTG_DIEPMSK (USBOTG_LINK_BASE + 0x810) /* Device IN Endpoint Common Interrupt Mask */
#define S3C_OTG_DOEPMSK (USBOTG_LINK_BASE + 0x814) /* Device OUT Endpoint Common Interrupt Mask */
#define S3C_OTG_DAINT (USBOTG_LINK_BASE + 0x818) /* Device All Endpoints Interrupt */
#define S3C_OTG_DAINTMSK (USBOTG_LINK_BASE + 0x81C) /* Device All Endpoints Interrupt Mask */
#define S3C_OTG_DTKNQR1 (USBOTG_LINK_BASE + 0x820) /* Device IN Token Sequence Learning Queue Read 1 */
#define S3C_OTG_DTKNQR2 (USBOTG_LINK_BASE + 0x824) /* Device IN Token Sequence Learning Queue Read 2 */
#define S3C_OTG_DVBUSDIS (USBOTG_LINK_BASE + 0x828) /* Device VBUS Discharge Time */
#define S3C_OTG_DVBUSPULSE (USBOTG_LINK_BASE + 0x82C) /* Device VBUS Pulsing Time */
#define S3C_OTG_DTKNQR3 (USBOTG_LINK_BASE + 0x830) /* Device IN Token Sequence Learning Queue Read 3 */
#define S3C_OTG_DTKNQR4 (USBOTG_LINK_BASE + 0x834) /* Device IN Token Sequence Learning Queue Read 4 */
/* Device Logical IN Endpoint-Specific Registers */
#define S3C_OTG_DIEPCTL0 (USBOTG_LINK_BASE + 0x900) /* Device IN Endpoint 0 Control */
#define S3C_OTG_DIEPINT0 (USBOTG_LINK_BASE + 0x908) /* Device IN Endpoint 0 Interrupt */
#define S3C_OTG_DIEPTSIZ0 (USBOTG_LINK_BASE + 0x910) /* Device IN Endpoint 0 Transfer Size */
#define S3C_OTG_DIEPDMA0 (USBOTG_LINK_BASE + 0x914) /* Device IN Endpoint 0 DMA Address */
/* Device Logical OUT Endpoint-Specific Registers */ #define S3C_OTG_DOEPCTL0 (USBOTG_LINK_BASE + 0xB00) /* Device OUT Endpoint 0 Control */
#define S3C_OTG_DOEPINT0 (USBOTG_LINK_BASE + 0xB08) /* Device OUT Endpoint 0 Interrupt */
#define S3C_OTG_DOEPTSIZ0 (USBOTG_LINK_BASE + 0xB10) /* Device OUT Endpoint 0 Transfer Size */
#define S3C_OTG_DOEPDMA0 (USBOTG_LINK_BASE + 0xB14) /* Device OUT Endpoint 0 DMA Address */
/* Power & clock gating registers */
#define S3C_OTG_PCGCCTRL (USBOTG_LINK_BASE + 0xE00)
/* Endpoint FIFO address */
#define S3C_OTG_EP0_FIFO (USBOTG_LINK_BASE + 0x1000)
/* OTG PHY CORE REGISTERS */
#define S3C_OTG_PHYPWR (USBOTG_PHY_BASE+0x00) #define S3C_OTG_PHYCTRL (USBOTG_PHY_BASE+0x04) #define S3C_OTG_RSTCON (USBOTG_PHY_BASE+0x08)
/* include common stuff */
/* watchdog */
#define WTCON_OFFSET 0x00
/* LCD controller */
#define LCDBGCON_OFFSET 0x5c
/* PENDING BIT */
#define BIT_EINT0 (0x1) #define BIT_EINT1 (0x1<<1) #define BIT_EINT2 (0x1<<2) #define BIT_EINT3 (0x1<<3) #define BIT_EINT4_7 (0x1<<4) #define BIT_EINT8_23 (0x1<<5) #define BIT_BAT_FLT (0x1<<7) #define BIT_TICK (0x1<<8) #define BIT_WDT (0x1<<9) #define BIT_TIMER0 (0x1<<10) #define BIT_TIMER1 (0x1<<11) #define BIT_TIMER2 (0x1<<12) #define BIT_TIMER3 (0x1<<13) #define BIT_TIMER4 (0x1<<14) #define BIT_UART2 (0x1<<15) #define BIT_LCD (0x1<<16) #define BIT_DMA0 (0x1<<17) #define BIT_DMA1 (0x1<<18) #define BIT_DMA2 (0x1<<19) #define BIT_DMA3 (0x1<<20) #define BIT_SDI (0x1<<21) #define BIT_SPI0 (0x1<<22) #define BIT_UART1 (0x1<<23) #define BIT_USBH (0x1<<26) #define BIT_IIC (0x1<<27) #define BIT_UART0 (0x1<<28) #define BIT_SPI1 (0x1<<29) #define BIT_RTC (0x1<<30) #define BIT_ADC (0x1<<31) #define BIT_ALLMSK (0xFFFFFFFF)
////////////////////////////////////////vic define//////////////////// #define VIC0BASE 0x71200000 #define VIC1BASE 0x71300000
///////////////////////VIC0///////////////////