FPGA实现双向IO口与时钟芯片的例子(11)

output Done_Sig;

output RST;

output SCLK;

inout SIO;

parameter T0P5US = 5'd24;//50M*(0.5e-6)-1=24

reg [4:0]Count1;

always @ ( posedge CLK or negedge RSTn )

if( !RSTn )

Count1 <= 5'd0;

else if( Count1 == T0P5US )

Count1 <= 5'd0;

else if( Start_Sig[0] == 1'b1 || Start_Sig[1] == 1'b1 ) Count1 <= Count1 + 1'b1;

else

Count1 <= 5'd0;

reg [5:0]i;

reg [7:0]rData;

reg rSCLK;

reg rRST;

reg rSIO;

reg isOut;

reg isDone;

always @ ( posedge CLK or negedge RSTn )

if( !RSTn )