FPGA实现双向IO口与时钟芯片的例子(2)

always @ ( posedge CLK or negedge RSTn )

if( !RSTn )

begin

i <= 4'd0;

isStart <= 8'd0;

rData <= 8'd0;

rLED <= 4'd0;

end

else

case( i )

0:

if( Done_Sig ) begin isStart <= 8'd0; i <= i + 1'b1; end

else begin isStart <= 8'b1000_0000; rData <= 8'h00; end

1:

if( Done_Sig ) begin isStart <= 8'd0; i <= i + 1'b1; end

else begin isStart <= 8'b0100_0000; rData <= { 4'd1, 4'd2 }; end

2:

if( Done_Sig ) begin isStart <= 8'd0; i <= i + 1'b1; end

else begin isStart <= 8'b0010_0000; rData <= { 4'd2, 4'd2 }; end

3:

if( Done_Sig ) begin isStart <= 8'd0; i <= i + 1'b1; end

else begin isStart <= 8'b0001_0000; rData <= { 4'd2, 4'd2 }; end

4: