FPGA实现双向IO口与时钟芯片的例子(9)

else if( Start_Sig[7:3] ) // Write action

case( i )

0 :

if( Access_Done_Sig ) begin isStart <= 2'b00; i <= i + 1'b1; end

else begin isStart <= 2'b10; end

1 :

begin isDone <= 1'b1; i <= i + 1'b1; end

2 :

begin isDone <= 1'b0; i <= 2'd0; end

endcase

else if( Start_Sig[2:0] ) // Read action

case( i )

0 :

if( Access_Done_Sig ) begin rRead <= Read_Data; isStart <= 2'b00; i <= i + 1'b1; end

else begin isStart <= 2'b01; end

1 :

begin isDone <= 1'b1; i <= i + 1'b1; end

2 :

begin isDone <= 1'b0; i <= 2'd0; end

endcase