FPGA实现双向IO口与时钟芯片的例子(13)

19, 21, 23, 25, 27, 29, 31, 33 : if( Count1 == T0P5US ) i <= i + 1'b1;

else begin rSCLK <= 1'b1; end

34 :

begin rRST <= 1'b0; i <= i + 1'b1; end

35 :

begin isDone <= 1'b1; i <= i + 1'b1; end

36 :

begin isDone <= 1'b0; i <= 6'd0; end

endcase

else if( Start_Sig[0] )

case( i )

0 :

begin rSCLK <= 1'b0; rData <= Words_Addr; rRST <= 1'b1; isOut <= 1'b1; i <= i + 1'b1; end

1, 3, 5, 7, 9, 11, 13, 15 : if( Count1 == T0P5US ) i <= i + 1'b1;

else begin rSIO <= rData[ (i >>

1) ]; rSCLK <= 1'b0; end

2, 4, 6, 8, 10, 12, 14, 16 : if( Count1 == T0P5US ) i <= i + 1'b1;

else begin rSCLK <= 1'b1; end

17 :