硕 士 学 位 论 文
论文题目
高性能视频开发验证平台系统的设计__ 作者姓名 蒋清晓 指导教师 虞露教授 学科(专业) 通信与信息系统 所在学院 信息学院
提交日期 二○○六年二月
1
浙江大学硕士学位论文
High Performance Video Development and
Verification Platform
Written by
QingXiao Jiang
Directed by
Prof. Yu Lu
Department of Information Science and Electronic Engineering
Zhejiang University Hangzhou, 310027
P.R.China
February 2006
Submitted in conformity with the requirements for the degree of master
in Zhejiang University
摘 要
视频编解码技术在日新月异的飞速发展，为了迎合高速发展的多媒体和集成电路技术，现在的VLSI开发需要大大缩短其开发周期以提高竞争地位。一般来说，随着某个高级视频解码标准的提出，总会在第一时间有相应的硬件解码器结构。FPGA原型验证开发系统由于其相对于ASIC有着前期设计成本低，回避设计风险，便于功能验证等特点，在视频编解码系统开发中有着极大的应用空间。随着高性能视频编解码器的开发需求越来越高，对基于FPGA的高性能视频开发与原型验证系统的需求也越来越大。
本文提出了基于FPGA的高性能视频开发验证平台的设计，这一设计是在原有的MPEG-4编解码芯片开发系统的基础上进行开发和设计的，可以满足高性能视频编解码器开发的需求。其设计目标为H.264 high 4:4:4@4 AVS Jizhun@6.2 等高端的视频编解码器的开发，支持1920×1080（4:4:4）的分辨率。平台具有如下的特征使其具有针对高性能视频编解码器的开发能力：
? 大规模高速可编程逻辑资源用于开发高复杂度的视频编解码器 ? 大容量高速外存储器资源用于存储高分辨率的图像数据 ? 高速数据传输通道用于传输高带宽的码流数据 ? 多种视频输入输出接口以应付不同的开发需要 ? 多种测试手段和工具以测试开发使用
? 提供接口应用模块以提高开发验证的效率，缩短开发周期 ? 充分考虑兼容性，以应对不同目标要求的视频开发需求 由于上述的特性，平台有着相当广泛的应用领域。
本文还介绍了基于高性能视频开发验证平台进行的AVS D1解码器开发设计和AVS运动矢量预测模块AGU的开发设计。并介绍了对模块进行了纯软件环境和实现后验证的方法，以确保模块内部逻辑和在平台环境中工作的正确性。本文还给出了MPEG-4编解码芯片开发系统、高性能视频开发验证平台和SMIC 0.18μm 单元库三者在统一的约束条件下综合后的比较结果。
概括起来，本文的工作贡献包括以下方面：
1. 总结了高性能视频编解码器开发的需求, 总结了原有开发系统的优势以及其缺陷
和不足，并充分整合到新设计中；
2. 给出了基于FPGA的高性能视频开发与验证平台整体设计，设计充分体现了高性能
的特点，注重开发验证过程的便利性和兼容性；
3. 给出了在平台上模块开发进行软件验证和综合后验证的方法； 4. 在平台上进行了视频编解码器模块的开发和设计，并给出了新旧平台与标准单元库
之间综合的比较结果。
关键词：视频编解码器、开发验证平台、高性能
1
浙江大学硕士学位论文
ABSTRACT
Video coding technique is developing fastly in recent years. A short design period of VLSI is required for competition reasons. The FPGA based development and verification systems are very useful for many applications considering of its low-price and fast verification. With the development of new video coding standard, the complexity and circuit density of the video codecs are much higher than before. There is clear requirement for high-performance FPGA-based video development and verification system. This thesis introduces an FPGA based high performance video development and verification platform. This platform is designed based on the original MPEG-4 video codec ASIC development system. The high performance video development and verification platform aimed at H.264 high 4:4:4 Profile@ Level 4 or AVS Jizhun Profile@ Level 6.2 etc. video codec design and verification. It supports the resolution of 1920×1080(4:4:4). The key features for this platform are listed as follow,
? Large-scale and high-speed programmable logic, ? Large-scale and high-speed on-board memory ? High-speed data transaction port, ? Different type video in/out ports, ? Large-number of test ports and tools, ? Interface driving modules, and ? Compatibility to early version.
This thesis also introduces the development process of AVS D1 decoder and the AVS motion vector prediction module (AGU) based on this high performance video development and verification platform. The way of software and after-implementation verification processes of the AGU is also introduced. Finally, comparisons of synthesis with the same constrain are given among the MPEG-4 codec development system, high performance video development and verification platform and SMIC 0.18μm cell library.
Keywords：Video codec, Development and verification platform, High performance
浙江大学硕士学位论文
目 录
摘 要............................................................................................................................................... 1 ABSTRACT ...................................................................................................................................... 2 目 录............................................................................................................................................... 3 图表目录 ........................................................................................................................................... 5 第1章 绪 论 ................................................................................................................................. 7
1.1视频编码标准的发展 ......................................................................................................... 7 1.2视频编解码芯片开发 ......................................................................................................... 8
1.2.1视频编解码芯片开发方法 ...................................................................................... 9 1.2.2 ASIC设计流程 ........................................................................................................ 9 1.2.3 FPGA与ASIC设计 ................................................................................................ 10 1.2.4视频编解码器体系结构 ........................................................................................ 11 1.3 本研究的意义及论文主要内容 ...................................................................................... 13 第2章 MPEG-4编解码芯片开发系统 ....................................................................................... 14
2.1 MPEG-4编解码芯片开发系统简介 ............................................................................... 14
2.1.1 性能指标 ............................................................................................................... 14 2.1.2 框架结构 ............................................................................................................... 14 2.1.3 重要硬件模块设计 ............................................................................................... 16 2.2 MPEG-4专用结构视频解码芯片开发 ........................................................................... 18
2.2.1 MPEG-4专用结构解码芯片系统结构................................................................. 18 2.2.2 系统子模块设计 ................................................................................................... 19 2.2.3 MPEG-4专用结构视频解码芯片 ........................................................................ 20 2.3 MPEG-4专用解码芯片验证系统 ................................................................................... 21 2.4 MPEG-4编解码芯片开发系统的缺陷与不足................................................................ 23 2.5 本章小节 .......................................................................................................................... 24 第3章 高性能视频开发验证平台设计 ....................................................................................... 25
3.1 平台简介 .......................................................................................................................... 25
3.1.1 设计目标与应用范围 ........................................................................................... 25 3.1.2 框架结构 ............................................................................................................... 25 3.1.3 平台优势 ............................................................................................................... 27 3.2 平台硬件系统设计 .......................................................................................................... 28
3.2.1 母板 ....................................................................................................................... 28
3.2.1.1母板整体结构 ............................................................................................. 28 3.2.1.2 FPGA........................................................................................................ 30 3.2.1.3 DDR400 外存储器接口 ........................................................................ 31 3.2.1.4 SRAM/SDRAM外存储器接口 ............................................................. 32 3.2.1.5电源解决方案 ............................................................................................. 33 3.2.1.6输入输出与测试端口 ................................................................................. 37 3.2.2 子板 ....................................................................................................................... 38
3.2.2.1子板整体结构 ............................................................................................. 38