SPI Operation BY25Q80A
5.1.2 Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the /CS line to VCC via a suitable pull-up resistor.
In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have been High, prior to going Low to start the first operation. 5.1.3 Device Reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in operating ranges of page 51). When VCC has passed the POR threshold, the device is reset. 5.1.4 Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal Write cycle in progress).
5.2 Active Power and Standby Power Modes
When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device consumes ICC.
When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops to ICC1.
5.3 Hold Condition
The Hold (/HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCLK) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (/CS) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress.
The Hold condition starts when the Hold (/HOLD) signal is driven Low at the same time as Serial Clock (SCLK) already being Low (as shown in Figure 4).
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The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 4 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (SCLK) being Low. Figure 4. Hold condition activation
/CSSCLK/HOLDHOLDHOLD
5.4 Status Register
5.4.1 Status Register Table
See Table 3 and Table 4 for detail description of the Status Register bits. Status Register-2 (SR2) and Status Register-1 (SR1) can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled the state of write protection, Quad SPI setting, Security Register lock status, and Erase/Program Suspend status. Table 3. Status Register-2 (SR2) BIT 7 6 5 4 3 2 1 Name SUS Function Default Value 0 0 0 0 0 0 0 Description 0 = Erase/Program not suspended 1 = Erase/Program suspended 0 = Normal Protection Map 1 = Inverted Protection Map OTP Lock Bits 3:1 for Security Registers 3:1 0 = Security Register not protected 1 = Security Register protected Suspend Status Complement CMP Protect LB3 Security LB2 Register Lock Bits LB1 Reserved Reserved QE Quad Enable Status Resister Protect 1 0 = Quad Mode Not Enabled, the /WP pin and /HOLD are enabled. 1 = Quad Mode Enabled, the IO2 and IO3 pins are enabled, and /WP and /HOLD functions are disabled 0 = SRP0 selects whether /WP input has effect on protection of the status register 1 = SRP0 selects Power Supply Lock Down or OTP Lock Down mode 0 SRP1 0
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Table 4. Status Register-1 (SR1) BIT 7 6 5 4 3 2 1 Name SRP0 SEC TB BP2 BP1 BP0 WEL Default Value 0 0 0 0 0 0 0 Description 0 = /WP input has no effect or Power Supply Lock Down mode 1 = /WP input can protect the Status Register or OTP Lock Down 0 = BP2-BP0 protect 64KB blocks 1 = BP2-BP0 protect 4KB sectors 0 = BP2-BP0 protect from the Top down 1 = BP2-BP0 protect from the Bottom up 000b = No protection See Table 6 and Table 7 for protection ranges 0 = Not Write Enabled, no embedded operation can start 1 = Write Enabled, embedded operation can start 0 = Not Busy, no embedded operation in progress 1 = Busy, embedded operation in progress Function Status Resister Protect 0 Sector/Block Protect Top/Bottom Protect Block Protect Bits Write Enable Latch Write in Progress Status 0 WIP 0
5.4.2 The Status and Control Bits 5.4.2.1 WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WIP bit sets 0, means the device is not in program/erase/write status register progress. 5.4.2.2 WEL bit
The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. 5.4.2.3 SEC, TB, BP2, BP1, BP0 bits
The Block Protect (SEC, TB, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register instruction. When the Block Protect (SEC, TB, BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in Table 6 and Table 7).becomes protected against Page Program, Sector Erase and Block Erase instructions. The Block Protect (SEC, TB, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
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5.4.2.4 SRP1, SRP0 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. 5.4.2.5 QE bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or ground).
5.4.2.6 LB3/LB2/LB1 bit
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register that provide the write protect control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the 256byte Security Registers will become read-only permanently, LB3/2/1 for Security Registers 3:1. 5.4.2.7 CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register2 (bit6). It is used in conjunction the SEC-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. 5.4.2.8 SUS bit
The SUS bit is a read only bit in the status register2 (bit7) that is set to 1 after executing an Erase/Program Suspend (75H) instruction. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) instruction as well as a power-down, power-up cycle.
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SPI Operation BY25Q80A
5.4.3 Status Register Protect Table Table 5. Status Register protect table SRP1 SRP0 /WP Status Register Software 0 0 X Protected Hardware 0 1 0 Protected Hardware 0 1 1 Unprotected 1 1 0 1 X X Power Supply Lock-Down(1) One Time Program (2) Description The Status Register can be written to after a Write Enable instruction, WEL=1.(Factory Default) /WP=0, the Status Register locked and cannot be written. /WP=1, the Status Register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and cannot be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and cannot be written to. Notes:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to
(0, 0) state.
2. The One time Program feature is available upon special order. Please contact Boya
Microelectronics for details.
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