Instructions Description BY25Q80A
7.2.2 Fast Read (0BH)
See Figure 11, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fc, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure 11. Fast Read Sequence Diagram /CS0SCLKInstructionSISO /CSSCLKDummy ClocksSISOHigh_ZData byte 176543210High_ZHigh_Z0BHHigh_Z 32333435363738394041424344454647 232224-Bit Address2132101234567891028293031
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Instructions Description BY25Q80A
7.2.3 Dual Output Fast Read (3BH)
See Figure 12, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure 12. Dual Output Fast Read Sequence Diagram
/CS0SCLKInstructionSISO/CS32SCLKSISODummy Clocks6745230167452301High_ZHigh_Z333435363738394041424344454647High_Z 3BH232224-Bit Address2132101234567891028293031 High_ZData Byte 1Data Byte 2
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Instructions Description BY25Q80A
7.2.4 Quad Output Fast Read (6BH)
See Figure 13, the Quad Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure 13. Quad Output Fast Read Sequence Diagram
/CS0SCLKInstructionSI(IO0)SO(IO1)/WP(IO2)/HOLD(IO3)/CSSCLKSI(IO0)SO(IO1)/WP(IO2)/HOLD(IO3)Dummy Clocks4High_Z0404040High_Z323334356BHHigh_ZHigh_ZHigh_Z23222124-Bit Address32101234567891028293031 36373839404142434445464751515151High_ZHigh_Z62626262High_ZHigh_Z73Byte173Byte273Byte337Byte4High_Z
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Instructions Description BY25Q80A
7.2.5 Dual I/O Fast Read (BBH)
See Figure 14, the Dual I/O Fast Read instruction is similar to the Dual Output Fast Read instruction but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out.
Figure 14. Dual I/O Fast Read Sequence Diagram (Initial command or previous M5-4≠10)
/CS0SCLKInstructionSI(IO0)SO(IO1)BBHHigh_Z642064206420642012345678910111213141516171819202122237531753175317531A23-16/CSSCLKSI(IO0)SO(IO1)2324252627282930313233A15-8A7-0M7-03435363738396420642064206420High_Z7531753175317
Byte 1Byte 2 Byte 335Byte 41High_Z
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Instructions Description BY25Q80A
7.2.6 Dual I/O Fast Read with “Continuous Read Mode”
The Fast Read Dual I/O command can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O command through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O command (after /CS is raised and then lowered) does not require the BBH instruction code, as shown in Figure 15. This reduces the command sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset command can also be used to reset (M7-0) before issuing normal commands (see Continuous Read Mode Reset (FFH or FFFFH)).
Figure 15. Dual I/O Fast Read Sequence Diagram (Previous command set M5-4 =10)
/CSSCLKSI(IO0)SO(IO1)/CSSCLKSI(IO0) SO(IO1)06714223046754627086791011121314154201674201531A23-16531A15-853A7-053M7-015161718192021222324252627282930316742016742672014201046753Byte1531Byte253Byte353Byte4
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