Instructions Description BY25Q80A
7.2.7 Quad I/O Fast Read (EBH)
See Figure 16, the Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read instruction but with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register must be set to enable for the Quad I/O Fast read instruction.
Figure 16. Quad I/O Fast Read Sequence Diagram (Initial command or previous M5-4≠10)
/CS0SCLKSI(IO0)SO(IO1)/WP(IO2)/HOLD(IO3)InstructionEBHHigh_ZHigh_ZHigh_Z45601245601245601245670123Dummy456012456012123456789 10111213141516171819202122237373A23-16A15-873A7-073Byte173Byte2
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Instructions Description BY25Q80A
7.2.8 Quad I/O Fast Read with “Continuous Read Mode”
The Fast Read Quad I/O command can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 16, The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O command through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O command (after /CS is raised and then lowered) does not require the EBH instruction code, as shown in Figure 17, This reduces the command sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next command (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset command can also be used to reset (M7-0) before issuing normal commands (see Continuous Read Mode Reset (FFH or FFFFH)).
Figure 17. Quad I/O Fast Read Sequence Diagram (Previous command set M5-4 =10)
/CS0SCLKSI(IO0)SO(IO1)/WP(IO2)/HOLD(IO3)45670123124567012334456750123456760123789101112131415456012456012A23-16A15-8A7-0M7-0Dummy73Byte173Byte2
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Instructions Description BY25Q80A
7.2.9 Continuous Read Mode Reset (FFH or FFFFH)
The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O” and “Fast Read Quad I/O” Instructions to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus allowing more efficient XIP (execute in place) with this device family.
The “Continuous Read Mode” bits M7-0 are set by the Dual/Quad I/O Read Instructions. M5-4 are used to control whether the 8-bit SPI instruction code (BBh or EBh) is needed or not for the next instruction. When M5-4 = (1,0), the next instruction will be treated the same as the current Dual/Quad I/O Read instruction without needing the 8-bit instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI instruction mode, in which all instructions can be accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used. See Figure 18, the Continuous Read Mode Reset instruction (FFh or FFFFh) can be used to set M4 = 1, thus the device will release the Continuous Read Mode and return to normal SPI operation.
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The instruction is “FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in instruction “FFFFh
Figure 18. Continuous Read Mode Reset Sequence Diagram
/CS0SCLKSI(IO0)SO(IO1)/WP(IO2)/HOLD(IO3)123456789101112131415InstructionFFHDon’t CareDon’t CareDon’t CareFFFFH
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Instructions Description BY25Q80A
7.2.10 Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) instruction prior to EBh. The “Set Burst with Wrap” (77h) instruction can either enable or disable the “Wrap Around” feature for the following EBh instructions. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. Wrap bit W7 and the lower nibble W3-0 are not used.
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4=1. The default value of W4 upon power on is 1.
W4 = 0 W6 W5 Wrap Around 0 0 0 1 1 0 1 1 Yes Yes Yes Yes Wrap Length 8-byte 16-byte 32-byte 64-byte Wrap Around No No No No Wrap Length N/A N/A N/A N/A W4 =1 (DEFAULT)
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Instructions Description BY25Q80A
Figure 19. Set Burst with Wrap Command Sequence
/CS0SCLKSI(IO0)Instruction77HHigh_Z123456789101112131415xxxxxxxxxxxxxxxxxxxxxxxxW4xxxxHigh_ZSO(IO1)/WP(IO2)/HOLD(IO3)W5High_ZHigh_ZHigh_ZW6High_ZxHigh_ZByte1Byte2Byte3Byte4
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