Instructions Description BY25Q80A 7.3 ID and Security Instructions
7.3.1 Read Manufacture ID/ Device ID (90H)
See Figure 20, the Read Manufacturer/Device ID instruction is an alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific Device ID.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H” followed by a 24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be read first.
Figure 20. Read Manufacture ID/ Device ID Sequence Diagram /CS0SCLKInstructionSISO/CS3233343536SCLKSISO76Manufacturer ID54321076Device ID325410373839404142434445464790HHigh_Z24-Bit Address32232221101234567891028293031
March 2014 Rev 2.3 36 / 63
Instructions Description BY25Q80A
7.3.2 JEDEC ID (9FH)
The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The device identification indicates the memory type in the first byte, and the memory capacity of the device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The JEDEC ID instruction should not be issued while the device is in Deep Power-Down Mode. See Figure 21, he device is first selected by driving /CS to low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The JEDEC ID instruction is terminated by driving /CS to high at any time during data output. When /CS is driven high, the device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute instructions. Figure 21. JEDEC ID Sequence Diagram
/CSSCLKSISO/CSSCLKSISO7MSB01234567891011121314159FHInstruction7MSB6Manufacturer ID5432101617181920212223242526 2728293031Memory Type ID15-ID865432107MSB
Capacity ID7-ID06543210
March 2014 Rev 2.3 37 / 63
Instructions Description BY25Q80A
7.3.3 Deep Power-Down (B9H)
Although the standby current during normal operation is relatively low, standby current can be further reduced with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down (DPD) instruction especially useful for battery powered applications (see ICC1 and ICC2). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 22.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power down instruction will not be executed. After /CS is driven high, the power-down state will entered within the time duration of tDP. While in the power-down state only the Release from Deep Power-down / Device ID instruction, which restores the device to normal operation, will be recognized. All other Instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction also makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1. Figure 22. Deep Power-Down Sequence Diagram
/CS0SCLKInstructionSIB9HStand-by modePower-down mode1234567tDP
March 2014 Rev 2.3 38 / 63
Instructions Description BY25Q80A
7.3.4 Release from Deep Power-Down/Read Device ID (ABH)
The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be used to release the device from the Power-Down state or obtain the devices electronic identification (ID) number.
See Figure 23a, to release the device from the Power-Down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABH” and driving /CS high Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instruction are accepted. The /CS pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 23b. The Device ID value for the BY25Q80A is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high.
When used to release the device from the Power-Down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 23b, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instruction will be accepted. If the Release from Power-Down/Device ID instruction is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the instruction is ignored and will not have any effects on the current cycle.
Figure 23a. Release Power-Down Sequence Diagram
/CS0SCLKInstructionSIABHPower-down modeStand-by mode1234567tRES1Figure 23b. Release Power-Down/Read Device ID Sequence Diagram
/CSSCLKInstructionSISOABHHigh_Z3 Dummy Bytes232221MSBtRES2076MSBDevice ID354210Stand-by mode01234567892930313233343536373839Deep Power-down mode
March 2014 Rev 2.3 39 / 63
Instructions Description BY25Q80A
7.3.5 Read Security Registers (48H)
See Figure 24, the Read Security Registers instruction is similar to Fast Read instruction. The instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the instruction is completed by driving /CS high.
Address Security Registers 1 Security Registers 2 Security Registers 3 A23-A16 00H 00H 00H A15-A8 01H 02H 03H A7-A0 Byte Address Byte Address Byte Address Figure 24. Read Security Registers instruction Sequence Diagram
/CS0SCLKInstructionSISO/CS32333435363738394041424344454647SCLKDummy ByteSISO76543210Data Byte 11234567892829303124-Bit Address48HHigh_Z2322321076MSB543210
March 2014 Rev 2.3 40 / 63