Instructions Description BY25Q80A
Read Security Registers(6) Enable Reset Reset Device 48H 7Eh 99h A23-A16 A15-A8 A7-A0 dummy (D7-D0) Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3
3. Quad Output Data
IO0 = (D4, D0,…..) IO1 = (D5, D1,…..) IO2 = (D6, D2,…..) IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…)
6. Security Registers Address:
Security Register0: A23-A16=00h, A15-A8=00h, A7-A0= Byte Address; Security Register1: A23-A16=00h, A15-A8=01h, A7-A0= Byte Address; Security Register2: A23-A16=00h, A15-A8=02h, A7-A0= Byte Address; Security Register3: A23-A16=00h, A15-A8=03h, A7-A0= Byte Address;
Security Register 0 can be used to store the Flash Discoverable Parameters,
The feature is upon special order, please contact Boya Microelectronics for
details.
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Instructions Description BY25Q80A 7.1 Configuration and Status Instructions
7.1.1 Write Enable (06H)
See Figure 5, the Write Enable instruction is for setting the Write Enable Latch bit. The Write Enable Latch bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instruction. The Write Enable instruction sequence: /CS goes low sending the Write Enable instruction /CS goes high. Figure 5. Write Enable Sequence Diagram
/CS0SCLK12345677.1.2 Write Disable (04H)
See Figure 6, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write Disable instruction sequence: /CS goes low Sending the Write Disable instruction /CS goes high. The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions. Figure 6. Write Disable Sequence Diagram
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SISO/CS0SCLK12Instruction06HHigh_Z
34567 SISOInstruction04HHigh_Z
Instructions Description BY25Q80A
7.1.3 Read Status Register (05H or 35H)
See Figure 7 the Read Status Register (RDSR) instruction is for reading the Status Register. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously. For instruction code “05H”, the SO will output Status Register bits S7~S0. The instruction code “35H”, the SO will output Status Register bits S15~S8. Figure 7. Read Status Register Sequence Diagram
/CS0SCLKInstructionSI05H or 35HHigh_ZS7-S0 or S15-S8 out 76MSB54321076MSB5S7-S0 or S15-S8 out43210123456789101112131415SO
7.1.4 Write Status Register (01H)
See Figure 8, the Write Status Register instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable instruction must previously have been executed. After the Write Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register instruction has no effect on S15, S1 and S0 of the Status Register. /CS must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register instruction is not executed. If /CS is driven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. As soon as /CS is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch is reset. The Write Status Register instruction allows the user to change the values of the Block Protect (SEC, TB, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3. The Write Status Register instruction also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (/WP) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (/WP) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register instruction is not executed once the Hardware Protected Mode is entered.
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Instructions Description BY25Q80A
Figure 8. Write Status Register Sequence Diagram
/CS0SCLKInstructionSI SO01HHigh_Z 7MSB6Status Register in54321 10 1101514131298 1234567891011121314151617181920212223
7.1.5 Write Enable for Volatile Status Register (50H)
See Figure 9, the non-volatile Status Register bits can also be written to as volatile bits. During power up reset, the non-volatile Status Register bits are copied to a volatile version of the Status Register that is used during device operation. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to each Write Status Registers (01h) instruction. Write Enable for Volatile Status Register instruction will not set the Write Enable Latch bit, it is only valid for the next following Write Status Registers instruction, to change the volatile Status Register bit values. Figure 9. Write Enable for Volatile Status Register
/CS0SCLK1234567
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SISOInstruction50HHigh_Z
Instructions Description BY25Q80A 7.2 Read Instructions
7.2.1 Read Data (03H)
See Figure 10, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single command as long as the clock continues. The command is completed by driving /CS high. The whole memory can be read with a single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Normal read mode running up to 50MHz.
Figure 10. Read Data Bytes Sequence Diagram
/CSSCLKSI SO012345678910282930313233343536373839Instruction03HHigh_Z 2322MSB24-Bit Address2132106 5 High_Z2103Data Byte17MSB4
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