SPI Operation BY25Q80A
5.4.4 Write Protect Features
1. Software Protection: The Block Protect (SEC, TB, BP2, BP1, BP0) bits define the section of
the memory array that can be read but not change.
2. Hardware Protection: /WP going low to protected the BP0~SEC bits and SRP0~1 bits. 3. Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the
Release from deep Power-Down Mode instruction.
4. Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program,
Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction.
5.4.5 Status Register Memory Protection 5.4.5.1 Protect Table
Table 6. BY25Q80A Status Register Memory Protection (CMP=0) Status Register Content SEC TB BP2 BP1 BP0 Blocks X 0 0 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 X X 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 NONE 1 15 0 14 to 15 1 12 to 15 0 8 to 15 1 0 0 0 to 1 1 0 to 3 0 0 to 7 1 0 to 15 X 0 to 15 1 15 0 15 1 15 X 15 1 0 0 0 1 0 X 0 Memory Content Addresses NONE 0F0000H-0FFFFFH 0E0000H-0FFFFFH 0C0000H-0FFFFFH 080000H-0FFFFFH 000000H-00FFFFH 000000H-01FFFFH 000000H-03FFFFH 000000H-07FFFFH 000000H-0FFFFFH 000000H-0FFFFFH 0FF000H-0FFFFFH 0FE000H-0FFFFFH 0FC000H-0FFFFFH 0F8000H-0FFFFFH 000000H-000FFFH 000000H-001FFFH 000000H-003FFFH 000000H-007FFFH Density NONE 64KB 128KB 256KB 512KB 64KB 128KB 256KB 512KB 1MB 1MB 4KB 8KB 16KB 32KB 4KB 8KB 16KB 32KB Portion NONE Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 Lower 1/16 Lower 1/8 Lower 1/4 Lower 1/2 ALL ALL Top Block Top Block Top Block Top Block Bottom Block Bottom Block Bottom Block Bottom Block
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SPI Operation BY25Q80A
Table 7. BY25Q80A Status Register Memory Protection (CMP=1) Status Register Content SEC TB BP2 BP1 BP0 Blocks X 0 0 0 0 0 0 0 0 0 X 1 1 1 1 1 1 1 1 X 0 0 0 0 1 1 1 1 X X 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 X 1 0 1 X 1 0 1 X 0 to 15 0 to 14 0 to 13 0 to 11 0 to 7 1 to 15 2 to 15 4 to 15 8 to 15 NONE NONE 0 to 15 0 to 15 0 to 15 0 to 15 0 to 15 0 to 15 0 to 15 0 to 15 Memory Content Addresses 000000H-0FFFFFH 000000H-0EFFFFH 000000H-0DFFFFH 000000H-0BFFFFH 000000H-07FFFFH 010000H-0FFFFFH 020000H-0FFFFFH 040000H-0FFFFFH 080000H-0FFFFFH NONE NONE 000000H-0FEFFFH 000000H-0FDFFFH 000000H-0FBFFFH 000000H-0F7FFFH 001000H-0FFFFFH 002000H-0FFFFFH 004000H-0FFFFFH 008000H-0FFFFFH Density 1MB 960KB 896KB 768KB 512KB 960KB 896KB 768KB 512KB NONE NONE 1020KB 1016KB 1008KB 992KB Portion ALL Lower 15/16 Lower 17/8 Lower 3/4 Lower 1/2 Upper 15/16 Upper 7/8 Upper 3/4 Upper 1/2 NONE NONE L - 255/256 L - 127/128 L - 63/64 L - 31/32 1020KB U - 255/256 1016KB U - 127/128 1008KB 992KB U - 63/64 U - 31/32
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Device Identification BY25Q80A
6. Device Identification
Three legacy Instructions are supported to access device identification that can indicate the manufacturer, device type, and capacity (density). The returned data bytes provide the information as shown in the below table.
Table 8. BY25Q80A ID Definition table
Operation Code 9FH 90H ABH M7-M0 E0 E0 ID15-ID8 40 ID7-ID0 14 13 13
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Instructions Description BY25Q80A
7. Instructions Description
All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table 9, every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. /CS must be driven high after the last bit of the instruction sequence has been shifted in. For the instruction of Read, Fast Read, Read Status Register or Release from Deep Power Down, and Read Device ID, the shifted-in instruction sequence is followed by a data out sequence. /CS can be driven high after any bit of the data-out sequence is being shifted out.
For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is /CS must driven high when the number of clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
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Instructions Description BY25Q80A
Table 9. Instruction Set Table Instruction Name Byte 1 Write Enable 06H Write Disable 04H Read Status 05H Register-1 Read Status 35H Register-2 Write Enable for Volatile Status 50H Register Write Status Register 01H Read Data 03H Fast Read 0BH Dual Output Fast 3BH Read Dual I/O Fast Read Quad Output Fast Read Quad I/O Fast Read Set Burst with Wrap Continuous Read Reset Page Program Sector Erase Block Erase(32K) Block Erase(64K) Chip Erase Program/Erase Suspend Program/Erase Resume Deep Power-Down Release From Deep Power-Down, And Read Device ID Release From Deep Power-Down Manufacturer/ Device ID JEDEC ID Erase Security Registers(6) Program Security Registers(6) BBH 6BH EBH 77h FFH 02H 20H 52H D8H C7/60H 75H 7AH B9H ABH ABH 90H 9FH 44H 42H Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 (S7-S0) (S15-S8) (S15-S8) A15-A8 A15-A8 A15-A8 A7-A0 M7-M0(2) A15-A8 dummy dummy A7-A0 A7-A0 A7-A0 (D7-D0)(1) A7-A0 (D7-D0)(5) dummy (D7-D0) dummy dummy Next byte (D7-D0) (D7-D0)(1) (S7-S0) A23-A16 A23-A16 A23-A16 A23-A8(2) A23-A16 A23-A0 M7-M0(4) dummy FFH A23-A16 A23-A16 A23-A16 A23-A16 dummy (D7-D0)(3) A15-A8 A15-A8 A15-A8 A15-A8 A7-A0 A7-A0 A7-A0 A7-A0 W8-W0 (D7-D0) Next byte dummy dummy dummy (ID7-ID0) dummy (M7-M0) A23-A16 A23-A16 dummy (ID15-ID8) A15-A8 A15-A8 00H (ID7-ID0) A7-A0 A7-A0 (M7-M0) (ID7-ID0) (D7-D0) (D7-D0)
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